[PATCH v18 1/3] dt-bindings: pwm: opencores: Drop starfive compatibles and update maintainers

[Hal Feng]

> On 25.05.15 21:06, Conor Dooley wrote:
> On Fri, May 15, 2026 at 01:47:20PM +0800, Hal Feng wrote:
> > Each of the StarFive JH7100/JH7110/JH8100 SoCs has 8 OpenCores PTC IP
> > cores. One OpenCores PTC IP core can output one PWM channel. The only
> > difference among them is the register base address. There is no need
> > to add starfive compatibles to distinguish them.
> 
> NAK, that's not an acceptable reason to remove soc-specific compatibles.

Got it, because it will break Device Tree ABI.

Best regards,
Hal

> 
> pw-bot: changes-requested
> 
> >
> > I will maintain the pwm module in place of William.
> >
> > Signed-off-by: Hal Feng <hal.feng at starfivetech.com>
> > ---
> >  .../devicetree/bindings/pwm/opencores,pwm.yaml         | 10 +++-------
> >  1 file changed, 3 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
> > b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
> > index 52a59d245cdb..834fb17ec595 100644
> > --- a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
> > +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
> > @@ -7,7 +7,7 @@ $schema:
> http://devicetree.org/meta-schemas/core.yaml#
> >  title: OpenCores PWM controller
> >
> >  maintainers:
> > -  - William Qiu <william.qiu at starfivetech.com>
> > +  - Hal Feng <hal.feng at starfivetech.com>
> >
> >  description:
> >    The OpenCores PTC ip core contains a PWM controller. When operating
> > in PWM @@ -20,10 +20,6 @@ allOf:
> >  properties:
> >    compatible:
> >      items:
> > -      - enum:
> > -          - starfive,jh7100-pwm
> > -          - starfive,jh7110-pwm
> > -          - starfive,jh8100-pwm
> >        - const: opencores,pwm-v1
> >
> >    reg:
> > @@ -48,8 +44,8 @@ additionalProperties: false
> >  examples:
> >    - |
> >      pwm at 12490000 {
> > -        compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
> > -        reg = <0x12490000 0x10000>;
> > +        compatible = "opencores,pwm-v1";
> > +        reg = <0x12490000 0x10>;
> >          clocks = <&clkgen 181>;
> >          resets = <&rstgen 109>;
> >          #pwm-cells = <3>;
> > --
> > 2.43.2
> >