[PATCH v3 1/8] dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules

[Krzysztof Kozlowski]

On Wed, May 20, 2026 at 06:29:25PM -0700, Changhuang Liang wrote:
> Add documentation to describe StarFive JHB100 SoC System Controller
> Registers.
> 
> Add the PLL clocks for the sys0, per0, and per1 domains under syscon,
> as well as the PCIe RP reset.
> 
> Signed-off-by: Changhuang Liang <changhuang.liang at starfivetech.com>
> ---
>  .../soc/starfive/starfive,jhb100-syscon.yaml  | 114 ++++++++++++++++++
>  MAINTAINERS                                   |   5 +
>  .../dt-bindings/clock/starfive,jhb100-crg.h   |  12 ++
>  .../dt-bindings/reset/starfive,jhb100-crg.h   |   3 +

Probably you should have own headers, instead of reusing CRG - CRG does
not sound like syscon, so these look like difference devices.

Anyway, if you decide to keep them in one, don't change your mind later.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at oss.qualcomm.com>

Best regards,
Krzysztof