[PATCH 1/2] riscv: track effective hardware PTE A/D updates

[Andrew Jones]

On Tue, May 19, 2026 at 11:19:26AM +0800, Yunhui Cui wrote:
> Platforms with Svadu but without Svade are treated as always using
> hardware PTE A/D updates.

This is correct, but I've become sensitive to the word 'always' after
recently reviewing the svadu spec. We should probably change the text in
Documentation/devicetree/bindings/riscv/extensions.yaml to something
like 'assume Svadu to be enabled at boot' because chapter 16 of the spec
states

"""
If the Svadu extension is implemented, the menvcfg.ADUE field is writable.
If the hypervisor extension is additionally implemented, the henvcfg.ADUE
field is also writable.
"""

So, if ADUE is writable then it cannot be hardwired to 1, which means it
can be written to zero. Then, in 3.1.18, we have

"""
When ADUE=0, the implementation behaves as though Svade were implemented
for S-mode and G-stage address translation.
"""

which means a spec-compliant system can never have svadu without svade.

Thanks,
drew