[PATCH 1/2] riscv: track effective hardware PTE A/D updates

[Conor Dooley]

On Tue, May 19, 2026 at 12:34:44PM -0500, Samuel Holland wrote:

> >>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> >>> index f46aa5602d74d..e46b2d2b49eed 100644
> >>> --- a/arch/riscv/kernel/cpufeature.c
> >>> +++ b/arch/riscv/kernel/cpufeature.c
> >>> @@ -35,6 +35,8 @@
> >>>   static bool any_cpu_has_zicboz;
> >>>   static bool any_cpu_has_zicbop;
> >>>   static bool any_cpu_has_zicbom;
> >>> +bool riscv_hw_pte_ad_updating_enabled __read_mostly;
> >>> +EXPORT_SYMBOL_GPL(riscv_hw_pte_ad_updating_enabled);
> >>>   unsigned long elf_hwcap __read_mostly;
> >>> @@ -287,15 +289,74 @@ static int riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data *data,
> >> ...
> >>> +static int __init riscv_hw_pte_ad_updating_init(void)
> >>> +{
> >>> +	bool has_svade, has_svadu;
> >>> +	int state;
> >>> +
> >>> +	has_svade = riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADE);
> >>> +	has_svadu = riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);
> >>> +
> >>> +	if (!has_svadu)
> >>> +		return 0;
> >>> +
> >>> +	if (!has_svade) {
> >>> +		riscv_set_hw_pte_ad_updating(true);
> >>> +		pr_info("riscv: hardware PTE A/D updating enabled\n");
> >>> +		return 0;
> >>
> >> This block is identical to the tail of the function. I'd probably use "goto
> >> enable", with an "enable" label below.
> > 
> > Is this code correct though? On DT systems, !svade && !svadu means we
> > don't actually know if it is hardware or software managed, so printing
> > that it's hardware managed may not be correct.
> > 
> > I don't understand the mm code enough to know if arch_has_hw_pte_young()
> > returning true is problematic too, but it probably is?
> 
> This block is for !svade && svadu (Svadu is present; we didn't return above), so
> I think this block and Michael's comment are correct.

D'oh... My bad!

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