[PATCH v18 3/3] pwm: Add OpenCores PTC PWM driver
Hal Feng
hal.feng at starfivetech.com
Thu May 14 22:47:22 PDT 2026
Add PWM driver for OpenCores PTC IP core.
Signed-off-by: Hal Feng <hal.feng at starfivetech.com>
---
MAINTAINERS | 6 +
drivers/pwm/Kconfig | 12 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-ocores.c | 249 +++++++++++++++++++++++++++++++++++++++
4 files changed, 268 insertions(+)
create mode 100644 drivers/pwm/pwm-ocores.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 6aa3fe2ee1bb..14af609f4ada 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20027,6 +20027,12 @@ F: Documentation/i2c/busses/i2c-ocores.rst
F: drivers/i2c/busses/i2c-ocores.c
F: include/linux/platform_data/i2c-ocores.h
+OPENCORES PWM DRIVER
+M: Hal Feng <hal.feng at starfivetech.com>
+S: Supported
+F: Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
+F: drivers/pwm/pwm-ocores.c
+
OPENRISC ARCHITECTURE
M: Jonas Bonn <jonas at southpole.se>
M: Stefan Kristiansson <stefan.kristiansson at saunalahti.fi>
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 6f3147518376..dd7f3bf5c3eb 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -534,6 +534,18 @@ config PWM_NTXEC
controller found in certain e-book readers designed by the original
design manufacturer Netronix.
+config PWM_OCORES
+ tristate "OpenCores PTC PWM support"
+ depends on HAS_IOMEM && OF
+ depends on COMMON_CLK
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ help
+ PWM driver for OpenCores PTC IP core.
+ For details see https://opencores.org/projects/ptc.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-ocores.
+
config PWM_OMAP_DMTIMER
tristate "OMAP Dual-Mode Timer PWM support"
depends on OF
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 0dc0d2b69025..2d47bad7bd74 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o
obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o
+obj-$(CONFIG_PWM_OCORES) += pwm-ocores.o
obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o
obj-$(CONFIG_PWM_PXA) += pwm-pxa.o
diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c
new file mode 100644
index 000000000000..fa6a34117cde
--- /dev/null
+++ b/drivers/pwm/pwm-ocores.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * OpenCores PTC PWM Driver
+ *
+ * https://opencores.org/projects/ptc
+ *
+ * Copyright (C) 2018-2026 StarFive Technology Co., Ltd.
+ *
+ * Limitations:
+ * - The hardware only supports inverted polarity.
+ * - The hardware minimum period / duty_cycle of PWM is (1 / pwm_apb clock frequency).
+ * - The hardware maximum period / duty_cycle of PWM is (U32_MAX / pwm_apb clock frequency).
+ * - The output is immediately set to low when the module is disabled.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/pwm.h>
+#include <linux/reset.h>
+
+#define OCPWM_HRC 0x4
+#define OCPWM_LRC 0x8
+#define OCPWM_CTRL 0xC
+
+#define OCPWM_CTRL_EN BIT(0)
+#define OCPWM_CTRL_OE BIT(3)
+#define OCPWM_CTRL_RST BIT(7)
+
+struct ocores_pwm_device {
+ void __iomem *base;
+ struct clk *clk;
+ unsigned long clk_rate;
+ struct reset_control *rst;
+};
+
+static int ocores_pwm_get_state(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct ocores_pwm_device *ddata = pwmchip_get_drvdata(chip);
+ u32 period_data, duty_data, ctrl_data;
+ int ret;
+
+ ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
+ if (ret < 0)
+ return ret;
+
+ period_data = readl(ddata->base + OCPWM_LRC);
+ duty_data = readl(ddata->base + OCPWM_HRC);
+ ctrl_data = readl(ddata->base + OCPWM_CTRL);
+
+ state->period = DIV_ROUND_UP_ULL((u64)period_data * NSEC_PER_SEC, ddata->clk_rate);
+ state->duty_cycle = DIV_ROUND_UP_ULL((u64)duty_data * NSEC_PER_SEC, ddata->clk_rate);
+ if (state->duty_cycle > state->period)
+ state->duty_cycle = state->period;
+
+ state->polarity = PWM_POLARITY_INVERSED;
+ state->enabled = (ctrl_data & OCPWM_CTRL_EN) ? true : false;
+
+ pm_runtime_put(pwmchip_parent(chip));
+
+ return 0;
+}
+
+static int ocores_pwm_apply(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct ocores_pwm_device *ddata = pwmchip_get_drvdata(chip);
+ u64 period_data, duty_data;
+ int ret;
+
+ if (state->polarity != PWM_POLARITY_INVERSED)
+ return -EINVAL;
+
+ if (state->enabled) {
+ if (!pwm_is_enabled(pwm)) {
+ ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
+ if (ret < 0)
+ return ret;
+ }
+ } else {
+ if (pwm_is_enabled(pwm)) {
+ writel(0, ddata->base + OCPWM_CTRL);
+ pm_runtime_put(pwmchip_parent(chip));
+ }
+ return 0;
+ }
+
+ writel(0, ddata->base + OCPWM_CTRL);
+ writel(OCPWM_CTRL_RST, ddata->base + OCPWM_CTRL);
+
+ period_data = mul_u64_u32_div(state->period, ddata->clk_rate, NSEC_PER_SEC);
+ if (period_data > U32_MAX)
+ period_data = U32_MAX;
+
+ duty_data = mul_u64_u32_div(state->duty_cycle, ddata->clk_rate, NSEC_PER_SEC);
+ if (duty_data > U32_MAX)
+ duty_data = U32_MAX;
+
+ writel(period_data, ddata->base + OCPWM_LRC);
+ writel(duty_data, ddata->base + OCPWM_HRC);
+ writel(OCPWM_CTRL_OE | OCPWM_CTRL_EN, ddata->base + OCPWM_CTRL);
+
+ return 0;
+}
+
+static const struct pwm_ops ocores_pwm_ops = {
+ .get_state = ocores_pwm_get_state,
+ .apply = ocores_pwm_apply,
+};
+
+static int ocores_pwm_runtime_suspend(struct device *dev)
+{
+ struct ocores_pwm_device *ddata = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(ddata->clk);
+
+ return 0;
+}
+
+static int ocores_pwm_runtime_resume(struct device *dev)
+{
+ struct ocores_pwm_device *ddata = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_prepare_enable(ddata->clk);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to enable clock\n");
+
+ return 0;
+}
+
+static const struct dev_pm_ops ocores_pwm_pm_ops = {
+ RUNTIME_PM_OPS(ocores_pwm_runtime_suspend,
+ ocores_pwm_runtime_resume, NULL)
+ SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+};
+
+static void ocores_pwm_pm_disable(void *data)
+{
+ struct device *dev = data;
+ struct ocores_pwm_device *ddata = dev_get_drvdata(dev);
+
+ pm_runtime_disable(dev);
+
+ if (!pm_runtime_status_suspended(dev))
+ ocores_pwm_runtime_suspend(dev);
+
+ reset_control_assert(ddata->rst);
+}
+
+static int ocores_pwm_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct ocores_pwm_device *ddata;
+ struct pwm_chip *chip;
+ int ret;
+
+ chip = devm_pwmchip_alloc(dev, 1, sizeof(*ddata));
+ if (IS_ERR(chip))
+ return -ENOMEM;
+
+ chip->ops = &ocores_pwm_ops;
+ ddata = pwmchip_get_drvdata(chip);
+
+ ddata->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(ddata->base))
+ return dev_err_probe(dev, PTR_ERR(ddata->base),
+ "Failed to map IO resources\n");
+
+ ddata->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(ddata->clk))
+ return dev_err_probe(dev, PTR_ERR(ddata->clk),
+ "Failed to get clock\n");
+
+ ddata->clk_rate = clk_get_rate(ddata->clk);
+ if (!ddata->clk_rate || ddata->clk_rate > NSEC_PER_SEC)
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid clock rate: %lu\n", ddata->clk_rate);
+
+ ddata->rst = devm_reset_control_get_optional_shared(dev, NULL);
+ if (IS_ERR(ddata->rst))
+ return dev_err_probe(dev, PTR_ERR(ddata->rst),
+ "Failed to get reset\n");
+
+ platform_set_drvdata(pdev, ddata);
+
+ ret = ocores_pwm_runtime_resume(dev);
+ if (ret)
+ return ret;
+
+ ret = reset_control_deassert(ddata->rst);
+ if (ret)
+ goto err_clk_disable;
+
+ ret = pm_runtime_set_active(dev);
+ if (ret)
+ goto err_reset_assert;
+
+ pm_runtime_enable(dev);
+
+ ret = devm_add_action_or_reset(dev, ocores_pwm_pm_disable, dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to add pm disable action\n");
+
+ pm_runtime_get_noresume(dev);
+
+ writel(0, ddata->base + OCPWM_CTRL);
+
+ pm_runtime_put(dev);
+
+ ret = devm_pwmchip_add(dev, chip);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Could not register PWM chip\n");
+
+ return 0;
+
+err_reset_assert:
+ reset_control_assert(ddata->rst);
+err_clk_disable:
+ ocores_pwm_runtime_suspend(dev);
+ return dev_err_probe(dev, ret, "Failed to init pwm power\n");
+}
+
+static const struct of_device_id ocores_pwm_of_match[] = {
+ { .compatible = "opencores,pwm-v1" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ocores_pwm_of_match);
+
+static struct platform_driver ocores_pwm_driver = {
+ .probe = ocores_pwm_probe,
+ .driver = {
+ .name = "ocores-pwm",
+ .of_match_table = ocores_pwm_of_match,
+ .pm = pm_ptr(&ocores_pwm_pm_ops),
+ },
+};
+module_platform_driver(ocores_pwm_driver);
+
+MODULE_AUTHOR("Jieqin Chen");
+MODULE_AUTHOR("Hal Feng <hal.feng at starfivetech.com>");
+MODULE_DESCRIPTION("OpenCores PTC PWM driver");
+MODULE_LICENSE("GPL");
--
2.43.2
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