[PATCH 5/9] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000
Jia Wang via B4 Relay
devnull+wangjia.ultrarisc.com at kernel.org
Thu May 14 18:18:01 PDT 2026
From: Jia Wang <wangjia at ultrarisc.com>
Add the base device tree for the UltraRISC DP1000 SoC. It describes the
8×CP100 CPU cores and essential SoC peripherals including the interrupt
controller, pinctrl, GPIO, UART, SPI, I2C, PCIe, GMAC and the DMA
controller.
Link: https://lore.kernel.org/lkml/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com/
Link: https://lore.kernel.org/lkml/20260429-ultrarisc-serial-v7-3-e475cce9e274@ultrarisc.com/
Signed-off-by: Jia Wang <wangjia at ultrarisc.com>
---
MAINTAINERS | 1 +
arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 851 ++++++++++++++++++++++++++++++
2 files changed, 852 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index baaaa46b1a56..832e01898ae5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23087,6 +23087,7 @@ M: Jia Wang <wangjia at ultrarisc.com>
L: linux-riscv at lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/riscv/ultrarisc.yaml
+F: arch/riscv/boot/dts/ultrarisc/
RNBD BLOCK DRIVERS
M: Md. Haris Iqbal <haris.iqbal at ionos.com>
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi
new file mode 100644
index 000000000000..1aae53fc1a2b
--- /dev/null
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi
@@ -0,0 +1,851 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+/dts-v1/;
+
+/ {
+ compatible = "ultrarisc,dp1000";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <10000000>;
+
+ cpu0: cpu at 0 {
+ compatible = "ultrarisc,cp100", "riscv";
+ reg = <0x0>;
+ device_type = "cpu";
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+ "zba", "zbb", "zbc", "zbs", "zicntr",
+ "zicsr", "zifencei", "zihpm", "ziccif",
+ "ziccrse", "ziccamoa", "za64rs", "zicbom",
+ "zicbop", "zicboz", "zkt", "svade",
+ "ssccptr", "sstvecd", "sscounterenw",
+ "shcounterenw", "shtvala", "shvstvecd",
+ "shvsatpa", "svvptc";
+ mmu-type = "riscv,sv48";
+ clock-frequency = <2000000000>;
+ /* L1 I-cache and D-cache:
+ * block-size 64B
+ * 4-way set associative, size 64KB
+ * per-core.
+ */
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+ next-level-cache = <&l2_cache0>;
+ riscv,cbom-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <0x01>;
+ };
+
+ l2_cache0: l2-cache {
+ /* L2 cache:
+ * cache-unified, block-size 64B
+ * 8-way set associative, size 512KB
+ * per-core.
+ */
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&cluster0_l3>;
+ };
+ };
+
+ cpu1: cpu at 1 {
+ compatible = "ultrarisc,cp100", "riscv";
+ reg = <0x1>;
+ device_type = "cpu";
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+ "zba", "zbb", "zbc", "zbs", "zicntr",
+ "zicsr", "zifencei", "zihpm", "ziccif",
+ "ziccrse", "ziccamoa", "za64rs", "zicbom",
+ "zicbop", "zicboz", "zkt", "svade",
+ "ssccptr", "sstvecd", "sscounterenw",
+ "shcounterenw", "shtvala", "shvstvecd",
+ "shvsatpa", "svvptc";
+ mmu-type = "riscv,sv48";
+ clock-frequency = <2000000000>;
+ /* L1 I-cache and D-cache:
+ * block-size 64B
+ * 4-way set associative, size 64KB
+ * per-core.
+ */
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+ next-level-cache = <&l2_cache1>;
+ riscv,cbom-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <0x01>;
+ };
+
+ l2_cache1: l2-cache {
+ /* L2 cache:
+ * cache-unified, block-size 64B
+ * 8-way set associative, size 512KB
+ * per-core.
+ */
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&cluster0_l3>;
+ };
+ };
+
+ cpu2: cpu at 2 {
+ compatible = "ultrarisc,cp100", "riscv";
+ reg = <0x2>;
+ device_type = "cpu";
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+ "zba", "zbb", "zbc", "zbs", "zicntr",
+ "zicsr", "zifencei", "zihpm", "ziccif",
+ "ziccrse", "ziccamoa", "za64rs", "zicbom",
+ "zicbop", "zicboz", "zkt", "svade",
+ "ssccptr", "sstvecd", "sscounterenw",
+ "shcounterenw", "shtvala", "shvstvecd",
+ "shvsatpa", "svvptc";
+ mmu-type = "riscv,sv48";
+ clock-frequency = <2000000000>;
+ /* L1 I-cache and D-cache:
+ * block-size 64B
+ * 4-way set associative, size 64KB
+ * per-core.
+ */
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+ next-level-cache = <&l2_cache2>;
+ riscv,cbom-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <0x01>;
+ };
+
+ l2_cache2: l2-cache {
+ /* L2 cache:
+ * cache-unified, block-size 64B
+ * 8-way set associative, size 512KB
+ * per-core.
+ */
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&cluster0_l3>;
+ };
+ };
+
+ cpu3: cpu at 3 {
+ compatible = "ultrarisc,cp100", "riscv";
+ reg = <0x3>;
+ device_type = "cpu";
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+ "zba", "zbb", "zbc", "zbs", "zicntr",
+ "zicsr", "zifencei", "zihpm", "ziccif",
+ "ziccrse", "ziccamoa", "za64rs", "zicbom",
+ "zicbop", "zicboz", "zkt", "svade",
+ "ssccptr", "sstvecd", "sscounterenw",
+ "shcounterenw", "shtvala", "shvstvecd",
+ "shvsatpa", "svvptc";
+ mmu-type = "riscv,sv48";
+ clock-frequency = <2000000000>;
+ /* L1 I-cache and D-cache:
+ * block-size 64B
+ * 4-way set associative, size 64KB
+ * per-core.
+ */
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+ next-level-cache = <&l2_cache3>;
+ riscv,cbom-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <0x01>;
+ };
+
+ l2_cache3: l2-cache {
+ /* L2 cache:
+ * cache-unified, block-size 64B
+ * 8-way set associative, size 512KB
+ * per-core.
+ */
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&cluster0_l3>;
+ };
+ };
+
+ cpu4: cpu at 4 {
+ compatible = "ultrarisc,cp100", "riscv";
+ reg = <0x10>;
+ device_type = "cpu";
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+ "zba", "zbb", "zbc", "zbs", "zicntr",
+ "zicsr", "zifencei", "zihpm", "ziccif",
+ "ziccrse", "ziccamoa", "za64rs", "zicbom",
+ "zicbop", "zicboz", "zkt", "svade",
+ "ssccptr", "sstvecd", "sscounterenw",
+ "shcounterenw", "shtvala", "shvstvecd",
+ "shvsatpa", "svvptc";
+ mmu-type = "riscv,sv48";
+ clock-frequency = <2000000000>;
+ /* L1 I-cache and D-cache:
+ * block-size 64B
+ * 4-way set associative, size 64KB
+ * per-core.
+ */
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+ next-level-cache = <&l2_cache4>;
+ riscv,cbom-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+
+ cpu4_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <0x01>;
+ };
+
+ l2_cache4: l2-cache {
+ /* L2 cache:
+ * cache-unified, block-size 64B
+ * 8-way set associative, size 512KB
+ * per-core.
+ */
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&cluster1_l3>;
+ };
+ };
+ cpu5: cpu at 5 {
+ compatible = "ultrarisc,cp100", "riscv";
+ reg = <0x11>;
+ device_type = "cpu";
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+ "zba", "zbb", "zbc", "zbs", "zicntr",
+ "zicsr", "zifencei", "zihpm", "ziccif",
+ "ziccrse", "ziccamoa", "za64rs", "zicbom",
+ "zicbop", "zicboz", "zkt", "svade",
+ "ssccptr", "sstvecd", "sscounterenw",
+ "shcounterenw", "shtvala", "shvstvecd",
+ "shvsatpa", "svvptc";
+ mmu-type = "riscv,sv48";
+ clock-frequency = <2000000000>;
+ /* L1 I-cache and D-cache:
+ * block-size 64B
+ * 4-way set associative, size 64KB
+ * per-core.
+ */
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+ next-level-cache = <&l2_cache5>;
+ riscv,cbom-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+
+ cpu5_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <0x01>;
+ };
+
+ l2_cache5: l2-cache {
+ /* L2 cache:
+ * cache-unified, block-size 64B
+ * 8-way set associative, size 512KB
+ * per-core.
+ */
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&cluster1_l3>;
+ };
+ };
+ cpu6: cpu at 6 {
+ compatible = "ultrarisc,cp100", "riscv";
+ reg = <0x12>;
+ device_type = "cpu";
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+ "zba", "zbb", "zbc", "zbs", "zicntr",
+ "zicsr", "zifencei", "zihpm", "ziccif",
+ "ziccrse", "ziccamoa", "za64rs", "zicbom",
+ "zicbop", "zicboz", "zkt", "svade",
+ "ssccptr", "sstvecd", "sscounterenw",
+ "shcounterenw", "shtvala", "shvstvecd",
+ "shvsatpa", "svvptc";
+ mmu-type = "riscv,sv48";
+ clock-frequency = <2000000000>;
+ /* L1 I-cache and D-cache:
+ * block-size 64B
+ * 4-way set associative, size 64KB
+ * per-core.
+ */
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+ next-level-cache = <&l2_cache6>;
+ riscv,cbom-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+
+ cpu6_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <0x01>;
+ };
+
+ l2_cache6: l2-cache {
+ /* L2 cache:
+ * cache-unified, block-size 64B
+ * 8-way set associative, size 512KB
+ * per-core.
+ */
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&cluster1_l3>;
+ };
+ };
+
+ cpu7: cpu at 7 {
+ compatible = "ultrarisc,cp100", "riscv";
+ reg = <0x13>;
+ device_type = "cpu";
+ riscv,isa = "rv64imafdcbh";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h",
+ "zba", "zbb", "zbc", "zbs", "zicntr",
+ "zicsr", "zifencei", "zihpm", "ziccif",
+ "ziccrse", "ziccamoa", "za64rs", "zicbom",
+ "zicbop", "zicboz", "zkt", "svade",
+ "ssccptr", "sstvecd", "sscounterenw",
+ "shcounterenw", "shtvala", "shvstvecd",
+ "shvsatpa", "svvptc";
+ mmu-type = "riscv,sv48";
+ clock-frequency = <2000000000>;
+ /* L1 I-cache and D-cache:
+ * block-size 64B
+ * 4-way set associative, size 64KB
+ * per-core.
+ */
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+ next-level-cache = <&l2_cache7>;
+ riscv,cbom-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+
+ cpu7_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <0x01>;
+ };
+
+ l2_cache7: l2-cache {
+ /* L2 cache:
+ * cache-unified, block-size 64B
+ * 8-way set associative, size 512KB
+ * per-core.
+ */
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&cluster1_l3>;
+ };
+ };
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1: cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+
+ core1 {
+ cpu = <&cpu5>;
+ };
+
+ core2 {
+ cpu = <&cpu6>;
+ };
+
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cluster0_l3: l3-cache0 {
+ /* L3 cache:
+ * cache-unified, block-size 64B
+ * 16-way set associative, size 4MB
+ * per-cluster.
+ */
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <3>;
+ cache-size = <0x400000>;
+ cache-sets = <0x1000>;
+ cache-unified;
+ next-level-cache = <&l4_cache>;
+ };
+
+ cluster1_l3: l3-cache1 {
+ /* L3 cache:
+ * cache-unified, block-size 64B
+ * 16-way set associative, size 4MB
+ * per-cluster.
+ */
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <3>;
+ cache-size = <0x400000>;
+ cache-sets = <0x1000>;
+ cache-unified;
+ next-level-cache = <&l4_cache>;
+ };
+ };
+
+ clocks {
+ device_clk: device_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <62500000>;
+ #clock-cells = <0>;
+ };
+
+ timer_clk: timer_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ #clock-cells = <0>;
+ };
+
+ csr_clk: csr_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ l4_cache: l4-cache {
+ /* L4 cache:
+ * cache-unified, block-size 64B
+ * 16-way set associative, size 16MB
+ * shared by the SoC.
+ */
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <4>;
+ cache-size = <0x1000000>;
+ cache-sets = <0x4000>;
+ cache-unified;
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x4 0x00000000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+
+ clint: clint at 8000000 {
+ compatible = "sifive,clint0", "riscv,clint0";
+ reg = <0x00 0x8000000 0x00 0x100000>;
+ interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>,
+ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>,
+ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>,
+ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>,
+ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>,
+ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>,
+ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>,
+ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>;
+ };
+
+ plic: plic at 9000000 {
+ compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic";
+ reg = <0x00 0x9000000 0x00 0x4000000>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>,
+ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>,
+ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>,
+ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>,
+ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>,
+ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>,
+ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>,
+ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>;
+ riscv,ndev = <160>;
+ };
+
+ pmx0: pinmux at 11081000 {
+ compatible = "ultrarisc,dp1000-pinctrl";
+ reg = <0x0 0x11081000 0x0 0x1000>;
+ #pinctrl-cells = <2>;
+ };
+
+ gpio: gpio at 20200000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x0 0x20200000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "bus", "db";
+ clocks = <&csr_clk>, <&device_clk>;
+
+ gpio_a: gpio-port at 0 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <16>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <34>;
+ gpio-ranges = <&pmx0 0 0 16>;
+ };
+
+ gpio_b: gpio-port at 1 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <8>;
+ gpio-ranges = <&pmx0 16 0 8>;
+ };
+
+ gpio_c: gpio-port at 2 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <8>;
+ gpio-ranges = <&pmx0 24 0 8>;
+ };
+
+ gpio_d: gpio-port at 3 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <8>;
+ gpio-ranges = <&pmx0 32 0 8>;
+ };
+ };
+
+ uart0: serial at 20300000 {
+ compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart";
+ reg = <0x00 0x20300000 0x00 0x10000>;
+ interrupt-parent = <&plic>;
+ interrupts = <17>;
+ clock-frequency = <62500000>;
+ reg-io-width = <0x04>;
+ reg-shift = <0x02>;
+ };
+
+ uart1: serial at 20310000 {
+ compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart";
+ reg = <0x00 0x20310000 0x00 0x10000>;
+ interrupt-parent = <&plic>;
+ interrupts = <18>;
+ clock-frequency = <62500000>;
+ reg-io-width = <0x04>;
+ reg-shift = <0x02>;
+ };
+
+ uart2: serial at 20400000 {
+ compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart";
+ reg = <0x00 0x20400000 0x00 0x10000>;
+ interrupt-parent = <&plic>;
+ interrupts = <25>;
+ clock-frequency = <62500000>;
+ reg-io-width = <0x04>;
+ reg-shift = <0x02>;
+ };
+
+ uart3: serial at 20410000 {
+ compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart";
+ reg = <0x00 0x20410000 0x00 0x10000>;
+ interrupt-parent = <&plic>;
+ interrupts = <26>;
+ clock-frequency = <62500000>;
+ reg-io-width = <0x04>;
+ reg-shift = <0x02>;
+ };
+
+ spi0: spi at 20320000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x0 0x20320000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&device_clk>;
+ interrupt-parent = <&plic>;
+ interrupts = <19>;
+ num-cs = <3>;
+ };
+
+ spi1: spi at 20420000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x0 0x20420000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&device_clk>;
+ interrupt-parent = <&plic>;
+ interrupts = <27>;
+ num-cs = <3>;
+ };
+
+ i2c0: i2c at 20330000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x20330000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&device_clk>;
+ interrupt-parent = <&plic>;
+ interrupts = <20>;
+ };
+
+ i2c1: i2c at 20340000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x20340000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&device_clk>;
+ interrupt-parent = <&plic>;
+ interrupts = <21>;
+ };
+
+ i2c2: i2c at 20430000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x20430000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&device_clk>;
+ interrupt-parent = <&plic>;
+ interrupts = <28>;
+ };
+
+ i2c3: i2c at 20440000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x20440000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&device_clk>;
+ interrupt-parent = <&plic>;
+ interrupts = <29>;
+ };
+
+ pcie_x16: pcie at 21000000 {
+ compatible = "ultrarisc,dp1000-pcie";
+ reg = <0x0 0x21000000 0x0 0x01000000>,
+ <0x0 0x4fff0000 0x0 0x00010000>;
+ reg-names = "dbi", "config";
+ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>,
+ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>,
+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ num-lanes = <16>;
+ interrupt-parent = <&plic>;
+ interrupts = <43>, <44>, <45>, <46>, <47>;
+ interrupt-names = "msi", "inta", "intb", "intc", "intd";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>,
+ <0x0 0x0 0x0 0x2 &plic 45>,
+ <0x0 0x0 0x0 0x3 &plic 46>,
+ <0x0 0x0 0x0 0x4 &plic 47>;
+ };
+
+ pcie_x4a: pcie at 23000000 {
+ compatible = "ultrarisc,dp1000-pcie";
+ reg = <0x0 0x23000000 0x0 0x01000000>,
+ <0x0 0x6fff0000 0x0 0x00010000>;
+ reg-names = "dbi", "config";
+ ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>,
+ <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>,
+ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ num-lanes = <4>;
+ interrupt-parent = <&plic>;
+ interrupts = <63>, <64>, <65>, <66>, <67>;
+ interrupt-names = "msi", "inta", "intb", "intc", "intd";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>,
+ <0x0 0x0 0x0 0x2 &plic 65>,
+ <0x0 0x0 0x0 0x3 &plic 66>,
+ <0x0 0x0 0x0 0x4 &plic 67>;
+ };
+
+ pcie_x4b: pcie at 24000000 {
+ compatible = "ultrarisc,dp1000-pcie";
+ reg = <0x0 0x24000000 0x0 0x01000000>,
+ <0x0 0x7fff0000 0x0 0x00010000>;
+ reg-names = "dbi", "config";
+ ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>,
+ <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>,
+ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ num-lanes = <4>;
+ interrupt-parent = <&plic>;
+ interrupts = <73>, <74>, <75>, <76>, <77>;
+ interrupt-names = "msi", "inta", "intb", "intc", "intd";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>,
+ <0x0 0x0 0x0 0x2 &plic 75>,
+ <0x0 0x0 0x0 0x3 &plic 76>,
+ <0x0 0x0 0x0 0x4 &plic 77>;
+ };
+
+ ethernet: ethernet at 38000000 {
+ compatible = "snps,dwmac", "snps,dwmac-5.10a";
+ reg = <0x00 0x38000000 0x00 0x1000000>;
+ clocks = <&csr_clk>;
+ clock-names = "stmmaceth";
+ interrupt-parent = <&plic>;
+ interrupts = <84>;
+ interrupt-names = "macirq";
+ local-mac-address = [ff ff ff ff ff ff];
+ max-speed = <1000>;
+ phy-mode = "rgmii-id";
+ snps,txpbl = <8>;
+ snps,rxpbl = <8>;
+ };
+
+ dmac: dma-controller at 39000000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x0 0x39000000 0x0 0x400>;
+ clocks = <&device_clk>, <&device_clk>;
+ clock-names = "core-clk", "cfgr-clk";
+ #dma-cells = <1>;
+ dma-channels = <8>;
+ interrupt-parent = <&plic>;
+ interrupts = <152>;
+ snps,dma-masters = <1>;
+ snps,data-width = <4>;
+ snps,block-size = <512 512 512 512 512 512 512 512>;
+ snps,priority = <0 1 2 3 4 5 6 7>;
+ snps,axi-max-burst-len = <256>;
+ };
+ };
+};
--
2.34.1
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