[PATCH v2 15/22] pinctrl: starfive: Add StarFive JHB100 per1 controller driver
Changhuang Liang
changhuang.liang at starfivetech.com
Thu May 14 04:12:11 PDT 2026
Add pinctrl driver for StarFive JHB100 SoC Peripheral-1(per1) pinctrl
controller.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang at starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang at starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang at starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 12 ++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-per1.c | 165 ++++++++++++++++++
3 files changed, 178 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 1e1bfdf87c31..c3889a152f6c 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -67,6 +67,18 @@ config PINCTRL_STARFIVE_JHB100_PER0
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+config PINCTRL_STARFIVE_JHB100_PER1
+ tristate "StarFive JHB100 SoC Peripheral-1 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ depends on OF
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support Peripheral-1 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
config PINCTRL_STARFIVE_JHB100_SYS0
tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index f2bb0c35a2a0..6beef7e313ef 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c
new file mode 100644
index 000000000000..91dfa113ca06
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-1 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo at starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/pinctrl/starfive,jhb100-pinctrl.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+static const struct jhb100_pin_layout_desc jhb100_per1_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 36, .name = "gpio", .gpio_func_sel = 0 },
+ { 0xff },
+};
+
+static struct config_reg_layout_desc jhb100_per1_pinctr_rldesc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 32,
+ .drive_strength_2bit = { .shift = 0, .width = 2 },
+ .input_enable = { .shift = 2, .width = 1 },
+ .pull_down = { .shift = 3, .width = 1 },
+ .pull_up = { .shift = 4, .width = 1 },
+ .slew_rate = { .shift = 5, .width = 1 },
+ .schmitt_trigger_select = { .shift = 6, .width = 1 },
+ .reserved = { .shift = 7, .width = 8 },
+ .debounce_width = { .shift = 15, .width = 17 },
+ },
+ {
+ .pin_start = 32,
+ .pin_cnt = 4,
+ .input_enable = { .shift = 0, .width = 1 },
+ .mode_select = { .shift = 1, .width = 2 },
+ .pull_down = { .shift = 3, .width = 1 },
+ .pull_up = { .shift = 4, .width = 1 },
+ .open_drain_pull_up_sel = { .shift = 5, .width = 2 },
+ .schmitt_trigger_select = { .shift = 7, .width = 1 },
+ .reserved = { .shift = 8, .width = 7 },
+ .debounce_width = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct pinvref_desc pinvref_desc_per1[] = {
+ {
+ .name = "gpioe-spi",
+ .pin_grp = {
+ PADNUM_PER1_GPIO_C0,
+ PADNUM_PER1_GPIO_C1,
+ PADNUM_PER1_GPIO_C2,
+ PADNUM_PER1_GPIO_C3,
+ PADNUM_PER1_GPIO_C4
+ },
+ .num_pins = 5,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ .name = "gpioe-qspi0",
+ .pin_grp = {
+ PADNUM_PER1_GPIO_C5,
+ PADNUM_PER1_GPIO_C6,
+ PADNUM_PER1_GPIO_C7,
+ PADNUM_PER1_GPIO_C8,
+ PADNUM_PER1_GPIO_C9,
+ PADNUM_PER1_GPIO_C10,
+ PADNUM_PER1_GPIO_C11
+ },
+ .num_pins = 7,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ .name = "gpioe-qspi1",
+ .pin_grp = {
+ PADNUM_PER1_GPIO_C12,
+ PADNUM_PER1_GPIO_C13,
+ PADNUM_PER1_GPIO_C14,
+ PADNUM_PER1_GPIO_C15,
+ PADNUM_PER1_GPIO_C16,
+ PADNUM_PER1_GPIO_C17,
+ PADNUM_PER1_GPIO_C18,
+ PADNUM_PER1_GPIO_C19
+ },
+ .num_pins = 8,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ .name = "gpioe-qspi2",
+ .pin_grp = {
+ PADNUM_PER1_GPIO_C20,
+ PADNUM_PER1_GPIO_C21,
+ PADNUM_PER1_GPIO_C22,
+ PADNUM_PER1_GPIO_C23,
+ PADNUM_PER1_GPIO_C24,
+ PADNUM_PER1_GPIO_C25,
+ PADNUM_PER1_GPIO_C26,
+ PADNUM_PER1_GPIO_C27
+ },
+ .num_pins = 8,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ { NULL },
+};
+
+struct starfive_pinctrl_regs jhb100_per1_pinctrl_regs = {
+ .vref = { .reg = 0x00, .pv_desc = pinvref_desc_per1 },
+ .func_sel = { .reg = 0xbc, .width_per_pin = 2 },
+ .config = 0x14,
+ .output = 0xa4,
+ .output_en = 0xac,
+ .gpio_status = 0xb4,
+ .irq_en = 0xc8,
+ .irq_status = 0xd0,
+ .irq_clr = 0xd8,
+ .irq_trigger = 0xe0,
+ .irq_level = 0xe8,
+ .irq_both_edge = 0xf0,
+ .irq_edge = 0xf8,
+};
+
+static const struct jhb100_pinctrl_func_maps jhb100_func_maps_per1[] = {
+ { .func = "gpio", .val = 0 },
+ { .func = "i2c", .val = 1 },
+ { .func = "sfc", .val = 1 },
+ { .func = "sgpio", .val = 1,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER1_GPIO_C31) },
+ { .func = "sgpio", .val = 2,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER1_GPIO_C35) },
+ { .func = "spi", .val = 1 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_per1_pinctrl_info = {
+ .name = "jhb100-per1",
+ .pl_desc = jhb100_per1_pl_desc,
+ .crl_desc = jhb100_per1_pinctr_rldesc,
+ .regs = &jhb100_per1_pinctrl_regs,
+ .fmaps = jhb100_func_maps_per1,
+ .num_maps = ARRAY_SIZE(jhb100_func_maps_per1),
+};
+
+static const struct of_device_id jhb100_per1_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-per1-pinctrl",
+ .data = &jhb100_per1_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per1_pinctrl_of_match);
+
+static struct platform_driver jhb100_per1_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-per1-pinctrl",
+ .of_match_table = jhb100_per1_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_per1_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-1 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo at starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
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