[PATCH v2 22/22] riscv: dts: starfive: jhb100: Add pinctrl nodes
Changhuang Liang
changhuang.liang at starfivetech.com
Thu May 14 04:12:18 PDT 2026
Add pinctrl nodes for starfive JHB100 SoC. They contain
pinctrl_per0/pinctrl_per1/pinctrl_per2/pinctrl_per2pok/pinctrl_per3/
pinctrl_sys0/pinctrl_sys0h/pinctrl_sys1/pinctrl_sys2.
Simultaneously initialize the pinctrl hog configuration and add a
pinctrl reference for uart6.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang at starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang at starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang at starfivetech.com>
---
arch/riscv/boot/dts/starfive/jhb100-evb1.dts | 35 ++++
.../boot/dts/starfive/jhb100-pinctrl.dtsi | 188 ++++++++++++++++++
arch/riscv/boot/dts/starfive/jhb100.dtsi | 110 ++++++++++
3 files changed, 333 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dts b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts
index 462b6fb7953b..bffecc986b30 100644
--- a/arch/riscv/boot/dts/starfive/jhb100-evb1.dts
+++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts
@@ -4,6 +4,7 @@
*/
#include "jhb100.dtsi"
+#include "jhb100-pinctrl.dtsi"
/ {
model = "StarFive JHB100 EVB-1";
@@ -27,6 +28,40 @@ memory at 40000000 {
};
};
+&pinctrl_per0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpioe_i3c0_configs
+ &gpioe_i3c1_configs
+ &gpioe_i3c2_configs
+ &gpioe_i3c4_configs>;
+};
+
+&pinctrl_per1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpioe_spi_configs
+ &gpioe_qspi0_configs
+ &gpioe_qspi1_configs
+ &gpioe_qspi2_configs>;
+};
+
+&pinctrl_per2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpionw_configs>;
+};
+
+&pinctrl_per3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpios_configs>;
+};
+
+&pinctrl_sys2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpiow0_configs
+ &gpiow_inner_configs>;
+};
+
&uart6 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6_pins>;
};
diff --git a/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi b/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
new file mode 100644
index 000000000000..926e018165fe
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2025-2026 StarFive Technology Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/starfive,jhb100-pinctrl.h>
+
+&pinctrl_per0 {
+ gpioe_i3c0_configs: gpioe-i3c0-hog-grp {
+ gpioe-i3c0-hog-pins {
+ pins = <PADNUM_PER0_GPIO_B8
+ PADNUM_PER0_GPIO_B9
+ PADNUM_PER0_GPIO_B10
+ PADNUM_PER0_GPIO_B11
+ PADNUM_PER0_GPIO_B32
+ PADNUM_PER0_GPIO_B33>;
+ power-source = <JHB100_PINVREF_3_3V>;
+ };
+ };
+
+ gpioe_i3c1_configs: gpioe-i3c1-hog-grp {
+ gpioe-i3c1-hog-pins {
+ pins = <PADNUM_PER0_GPIO_B12
+ PADNUM_PER0_GPIO_B13
+ PADNUM_PER0_GPIO_B14
+ PADNUM_PER0_GPIO_B15
+ PADNUM_PER0_GPIO_B34
+ PADNUM_PER0_GPIO_B35>;
+ power-source = <JHB100_PINVREF_3_3V>;
+ };
+ };
+
+ gpioe_i3c2_configs: gpioe-i3c2-hog-grp {
+ gpioe-i3c2-hog-pins {
+ pins = <PADNUM_PER0_GPIO_B16
+ PADNUM_PER0_GPIO_B17
+ PADNUM_PER0_GPIO_B18
+ PADNUM_PER0_GPIO_B19
+ PADNUM_PER0_GPIO_B20
+ PADNUM_PER0_GPIO_B21
+ PADNUM_PER0_GPIO_B22
+ PADNUM_PER0_GPIO_B23>;
+ power-source = <JHB100_PINVREF_3_3V>;
+ };
+ };
+
+ gpioe_i3c4_configs: gpioe-i3c4-hog-grp {
+ gpioe-i3c4-hog-pins {
+ pins = <PADNUM_PER0_GPIO_B36
+ PADNUM_PER0_GPIO_B37
+ PADNUM_PER0_GPIO_B38
+ PADNUM_PER0_GPIO_B39
+ PADNUM_PER0_GPIO_B40
+ PADNUM_PER0_GPIO_B41
+ PADNUM_PER0_GPIO_B42
+ PADNUM_PER0_GPIO_B43>;
+ power-source = <JHB100_PINVREF_3_3V>;
+ };
+ };
+};
+
+&pinctrl_per1 {
+ gpioe_spi_configs: gpioe-spi-hog-grp {
+ gpioe-spi-hog-pins {
+ pins = <PADNUM_PER1_GPIO_C0
+ PADNUM_PER1_GPIO_C1
+ PADNUM_PER1_GPIO_C2
+ PADNUM_PER1_GPIO_C3
+ PADNUM_PER1_GPIO_C4>;
+ power-source = <JHB100_PINVREF_3_3V>;
+ };
+ };
+
+ gpioe_qspi0_configs: gpioe-qspi0-hog-grp {
+ gpioe-qspi0-hog-pins {
+ pins = <PADNUM_PER1_GPIO_C5
+ PADNUM_PER1_GPIO_C6
+ PADNUM_PER1_GPIO_C7
+ PADNUM_PER1_GPIO_C8
+ PADNUM_PER1_GPIO_C9
+ PADNUM_PER1_GPIO_C10
+ PADNUM_PER1_GPIO_C11>;
+ power-source = <JHB100_PINVREF_3_3V>;
+ };
+ };
+
+ gpioe_qspi1_configs: gpioe-qspi1-hog-grp {
+ gpioe-qspi1-hog-pins {
+ pins = <PADNUM_PER1_GPIO_C12
+ PADNUM_PER1_GPIO_C13
+ PADNUM_PER1_GPIO_C14
+ PADNUM_PER1_GPIO_C15
+ PADNUM_PER1_GPIO_C16
+ PADNUM_PER1_GPIO_C17
+ PADNUM_PER1_GPIO_C18
+ PADNUM_PER1_GPIO_C19>;
+ power-source = <JHB100_PINVREF_3_3V>;
+ };
+ };
+
+ gpioe_qspi2_configs: gpioe-qspi2-hog-grp {
+ gpioe-qspi2-hog-pins {
+ pins = <PADNUM_PER1_GPIO_C20
+ PADNUM_PER1_GPIO_C21
+ PADNUM_PER1_GPIO_C22
+ PADNUM_PER1_GPIO_C23
+ PADNUM_PER1_GPIO_C24
+ PADNUM_PER1_GPIO_C25
+ PADNUM_PER1_GPIO_C26
+ PADNUM_PER1_GPIO_C27>;
+ power-source = <JHB100_PINVREF_3_3V>;
+ };
+ };
+};
+
+&pinctrl_per2 {
+ gpionw_configs: gpionw-hog-grp {
+ gpionw-hog-pins {
+ pins = <PADNUM_PER2_GPIO_D19
+ PADNUM_PER2_GPIO_D20
+ PADNUM_PER2_GPIO_D21
+ PADNUM_PER2_GPIO_D22
+ PADNUM_PER2_GPIO_D23
+ PADNUM_PER2_GPIO_D24
+ PADNUM_PER2_GPIO_D25
+ PADNUM_PER2_GPIO_D26
+ PADNUM_PER2_GPIO_D27
+ PADNUM_PER2_GPIO_D28
+ PADNUM_PER2_GPIO_D29
+ PADNUM_PER2_GPIO_D30>;
+ power-source = <2>;
+ };
+ };
+};
+
+&pinctrl_per3 {
+ gpios_configs: gpios-hog-grp {
+ gpios-hog-pins {
+ pins = <PADNUM_PER3_GPIO_E0
+ PADNUM_PER3_GPIO_E1
+ PADNUM_PER3_GPIO_E2
+ PADNUM_PER3_GPIO_E3
+ PADNUM_PER3_GPIO_E4
+ PADNUM_PER3_GPIO_E5
+ PADNUM_PER3_GPIO_E6
+ PADNUM_PER3_GPIO_E7
+ PADNUM_PER3_GPIO_E8
+ PADNUM_PER3_GPIO_E9
+ PADNUM_PER3_GPIO_E10>;
+ power-source = <JHB100_PINVREF_1_8V>;
+ };
+ };
+};
+
+&pinctrl_sys2 {
+ gpiow0_configs: gpiow0-hog-grp {
+ gpiow0-hog-pins {
+ pins = <PADNUM_SYS2_GPIO_A36
+ PADNUM_SYS2_GPIO_A37
+ PADNUM_SYS2_GPIO_A38
+ PADNUM_SYS2_GPIO_A39>;
+ power-source = <JHB100_PINVREF_3_3V>;
+ };
+ };
+
+ gpiow_inner_configs: gpiow-inner-hog-grp {
+ gpiow-inner-hog-pins {
+ pins = <PADNUM_SYS2_GPIO_A40
+ PADNUM_SYS2_GPIO_A41
+ PADNUM_SYS2_GPIO_A42
+ PADNUM_SYS2_GPIO_A43>;
+ power-source = <JHB100_PINVREF_3_3V>;
+ };
+ };
+
+ uart6_pins: uart6-grp {
+ uart6-tx-pins {
+ pins = <PADNUM_SYS2_GPIO_A38>;
+ function = "uart";
+ };
+
+ uart6-rx-pins {
+ pins = <PADNUM_SYS2_GPIO_A39>;
+ function = "uart";
+ input-enable;
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
index 943324b3b2fd..f9a7fa9d37e3 100644
--- a/arch/riscv/boot/dts/starfive/jhb100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
@@ -428,6 +428,19 @@ per0crg: clock-controller at 11a08000 {
#reset-cells = <1>;
};
+ pinctrl_per0: pinctrl at 11a0a000 {
+ compatible = "starfive,jhb100-per0-pinctrl";
+ reg = <0x0 0x11a0a000 0x0 0x1000>;
+ resets = <&per0crg JHB100_PER0RST_GPIO_IOMUX_PRESETN>;
+ interrupts = <60>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ gpio-ranges = <&pinctrl_per0 0 0 0 32>,
+ <&pinctrl_per0 1 0 32 28>;
+ };
+
per1crg: clock-controller at 11b40000 {
compatible = "starfive,jhb100-per1crg";
reg = <0x0 0x11b40000 0x0 0x1000>;
@@ -443,6 +456,19 @@ per1crg: clock-controller at 11b40000 {
#reset-cells = <1>;
};
+ pinctrl_per1: pinctrl at 11b42000 {
+ compatible = "starfive,jhb100-per1-pinctrl";
+ reg = <0x0 0x11b42000 0x0 0x800>;
+ resets = <&per1crg JHB100_PER1RST_IOMUX_PRESETN>;
+ interrupts = <61>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ gpio-ranges = <&pinctrl_per1 0 0 0 32>,
+ <&pinctrl_per1 1 0 32 4>;
+ };
+
per2crg: clock-controller at 11bc0000 {
compatible = "starfive,jhb100-per2crg";
reg = <0x0 0x11bc0000 0x0 0x1000>;
@@ -464,6 +490,30 @@ per2crg: clock-controller at 11bc0000 {
#reset-cells = <1>;
};
+ pinctrl_per2: pinctrl at 11bc2000 {
+ compatible = "starfive,jhb100-per2-pinctrl";
+ reg = <0x0 0x11bc2000 0x0 0x400>;
+ resets = <&per2crg JHB100_PER2RST_IOMUX_PRESETN>;
+ interrupts = <62>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ gpio-ranges = <&pinctrl_per2 0 0 0 31>;
+ };
+
+ pinctrl_per2pok: pinctrl at 11bc2400 {
+ compatible = "starfive,jhb100-per2pok-pinctrl";
+ reg = <0x0 0x11bc2400 0x0 0x400>;
+ resets = <&per2crg JHB100_PER2RST_POK_IOMUX_PRESETN>;
+ interrupts = <63>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ gpio-ranges = <&pinctrl_per2pok 0 0 0 18>;
+ };
+
per3crg: clock-controller at 11c40000 {
compatible = "starfive,jhb100-per3crg";
reg = <0x0 0x11c40000 0x0 0x1000>;
@@ -483,6 +533,18 @@ per3crg: clock-controller at 11c40000 {
#reset-cells = <1>;
};
+ pinctrl_per3: pinctrl at 11c42000 {
+ compatible = "starfive,jhb100-per3-pinctrl";
+ reg = <0x0 0x11c42000 0x0 0x1000>;
+ resets = <&per3crg JHB100_PER3RST_IOMUX_PRESETN>;
+ interrupts = <64>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ gpio-ranges = <&pinctrl_per3 0 0 0 11>;
+ };
+
sys0crg: clock-controller at 13000000 {
compatible = "starfive,jhb100-sys0crg";
reg = <0x0 0x13000000 0x0 0x4000>;
@@ -517,6 +579,54 @@ sys2crg: clock-controller at 13008000 {
#reset-cells = <1>;
};
+ pinctrl_sys0: pinctrl at 13080000 {
+ compatible = "starfive,jhb100-sys0-pinctrl";
+ reg = <0x0 0x13080000 0x0 0x800>;
+ resets = <&sys0crg JHB100_SYS0RST_SYS0_IOMUX_PRESETN>;
+ interrupts = <56>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ gpio-ranges = <&pinctrl_sys0 0 0 0 4>;
+ };
+
+ pinctrl_sys0h: pinctrl at 13080800 {
+ compatible = "starfive,jhb100-sys0h-pinctrl";
+ reg = <0x0 0x13080800 0x0 0x800>;
+ resets = <&sys0crg JHB100_SYS0RST_SYS0H_IOMUX_PRESETN>;
+ interrupts = <57>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ gpio-ranges = <&pinctrl_sys0h 0 0 0 12>;
+ };
+
+ pinctrl_sys1: pinctrl at 13081000 {
+ compatible = "starfive,jhb100-sys1-pinctrl";
+ reg = <0x0 0x13081000 0x0 0x1000>;
+ resets = <&sys1crg JHB100_SYS1RST_SYS1_IOMUX_PRESETN>;
+ interrupts = <58>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ gpio-ranges = <&pinctrl_sys1 0 0 0 8>;
+ };
+
+ pinctrl_sys2: pinctrl at 13082000 {
+ compatible = "starfive,jhb100-sys2-pinctrl";
+ reg = <0x0 0x13082000 0x0 0x1000>;
+ interrupts = <59>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ gpio-ranges = <&pinctrl_sys2 0 0 0 32>,
+ <&pinctrl_sys2 1 0 32 5>;
+ };
+
intc: interrupt-controller at 13220000 {
compatible = "starfive,jhb100-intc";
reg = <0x0 0x13220000 0x0 0x80>;
--
2.25.1
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