[PATCH v2 2/4] clk: spacemit: k3: Fix PCIe clock register offset

[Conor Dooley]

On Mon, May 11, 2026 at 02:59:10AM +0000, Yixun Lan wrote:
> The offset of PCIe Clock CTRL register for port B and C controller was
> wrongly swapped, correct it here.
> 
> Fixes: 091d19cc2401 ("clk: spacemit: k3: extract common header")
> Signed-off-by: Yixun Lan <dlan at kernel.org>
> ---

Acked-by: Conor Dooley <conor.dooley at microchip.com>
pw-bot: not-applicable

>  include/soc/spacemit/k3-syscon.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h
> index 0299bea065a0..a68255dd641f 100644
> --- a/include/soc/spacemit/k3-syscon.h
> +++ b/include/soc/spacemit/k3-syscon.h
> @@ -168,8 +168,8 @@
>  #define APMU_CPU_C2_CLK_CTRL		0x394
>  #define APMU_CPU_C3_CLK_CTRL		0x208
>  #define APMU_PCIE_CLK_RES_CTRL_A	0x1f0
> -#define APMU_PCIE_CLK_RES_CTRL_B	0x1c8
> -#define APMU_PCIE_CLK_RES_CTRL_C	0x1d0
> +#define APMU_PCIE_CLK_RES_CTRL_B	0x1d0
> +#define APMU_PCIE_CLK_RES_CTRL_C	0x1c8
>  #define APMU_PCIE_CLK_RES_CTRL_D	0x1e0
>  #define APMU_PCIE_CLK_RES_CTRL_E	0x1e8
>  #define APMU_EMAC0_CLK_RES_CTRL		0x3e4
> 
> -- 
> 2.54.0
> 
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