[PATCH v2 00/10] riscv: hwprobe: Expose RVA23U64 base behavior
Guodong Xu
guodong at riscstar.com
Mon May 11 18:34:45 PDT 2026
This series builds on Andrew Jones's earlier RFC [1]. It lets
userspace check for RVA23U64 conformance in one call, instead of
walking hwprobe + prctl across every mandatory extension.
The series adds a small framework that resolves profile-class
bases (IMA and RVA23U64) from the kernel's ISA extension bitmap at
init time, and surfaces the result through both /proc/cpuinfo and
hwprobe. Later patches can add RVA23S64, and backward RVA22 / RVA20
detection, to riscv_set_isa_bases() without changes to the
surrounding code.
To detect RVA23U64 the kernel first has to recognise every extension
it mandates, so patches 4-6 bring Zicclsm; Ziccamoa, Ziccif,
Ziccrse, Za64rs; and B into the cpufeature parser. The framework
then reads the resulting bitmap, and the final patch exposes the
RVA23U64 bit through RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64.
Series outline:
1-3. hwprobe.rst clean-ups: document EXT_ZICFISS, normalize
indentation, and standardize extension capitalization.
4. Zicclsm: cpufeature parsing + hwprobe export.
5. Ziccamoa, Ziccif, Ziccrse, Za64rs: cpufeature parsing + hwprobe
export, with cpufeature dependency validation for
Ziccamoa->Zaamo and Za64rs->Zalrsc.
6. B (hwcap + hwprobe), as the Zba/Zbb/Zbs set.
7. riscv_have_user_pmlen(): arch-level accessor for user
pointer-masking PMLEN support, used by RVA23U64 detection.
8. cpufeature: per-hart and host-wide isa_bases bitmaps,
populated at init time. IMA and RVA23U64 detection lives
here; /proc/cpuinfo and hwprobe both read from these bitmaps.
9. /proc/cpuinfo: print "isa bases" / "hart isa bases" lines
sourced from the cached bitmaps.
10. hwprobe: expose RVA23U64 via
RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64.
Tested on qemu booted with -cpu rva23s64,sv39=on,pmp=on:
- /proc/cpuinfo reports "isa bases : rv64ima rva23u64" on both the
aggregated and per-hart lines.
- hwprobe RISCV_HWPROBE_KEY_BASE_BEHAVIOR returns
BASE_BEHAVIOR_IMA | BASE_BEHAVIOR_RVA23U64.
Based on v7.2-rc2; happy to rebase onto another tree if needed.
Link: https://lore.kernel.org/linux-riscv/20260206002349.96740-1-andrew.jones@oss.qualcomm.com/ [1]
BR,
Guodong Xu
Signed-off-by: Guodong Xu <guodong at riscstar.com>
---
Andrew Jones (4):
riscv: hwprobe.rst: Replace tabs with spaces
riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to cpufeature and hwprobe
riscv: Add B to hwcap and hwprobe
riscv: Add a getter for user PMLEN support
Charlie Jenkins (1):
riscv: Standardize extension capitalization
Guodong Xu (4):
riscv: hwprobe.rst: Document EXT_ZICFISS
riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection
riscv: cpu: Output isa bases lines in cpuinfo
riscv: hwprobe: Introduce rva23u64 base behavior
Jesse Taube (1):
riscv: Add Zicclsm to cpufeature and hwprobe
Documentation/arch/riscv/hwprobe.rst | 46 +++++-
arch/riscv/include/asm/cpufeature.h | 14 ++
arch/riscv/include/asm/hwcap.h | 23 +--
arch/riscv/include/asm/processor.h | 4 +
arch/riscv/include/asm/switch_to.h | 4 +-
arch/riscv/include/uapi/asm/hwcap.h | 1 +
arch/riscv/include/uapi/asm/hwprobe.h | 9 +-
arch/riscv/kernel/cpu.c | 26 ++++
arch/riscv/kernel/cpufeature.c | 154 ++++++++++++++++++---
arch/riscv/kernel/process.c | 12 ++
arch/riscv/kernel/sys_hwprobe.c | 33 +++--
arch/riscv/kvm/isa.c | 16 +--
arch/riscv/kvm/main.c | 2 +-
arch/riscv/kvm/vcpu_fp.c | 20 +--
arch/riscv/kvm/vcpu_onereg.c | 6 +-
arch/riscv/kvm/vcpu_vector.c | 10 +-
tools/testing/selftests/riscv/hwprobe/which-cpus.c | 2 +-
17 files changed, 312 insertions(+), 70 deletions(-)
---
base-commit: 7fd2df204f342fc17d1a0bfcd474b24232fb0f32
change-id: 20260508-rva23u64-hwprobe-v2-1d20739cbb8e
Best regards,
--
Guodong Xu <guodong at riscstar.com>
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