[PATCH v2 09/22] dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator
Changhuang Liang
changhuang.liang at starfivetech.com
Thu May 7 22:36:19 PDT 2026
Add bindings for the System-2 clocks and reset generator (SYS2CRG) on
JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang at starfivetech.com>
---
.../clock/starfive,jhb100-sys2crg.yaml | 64 +++++++++++++++++++
.../dt-bindings/clock/starfive,jhb100-crg.h | 33 ++++++++++
.../dt-bindings/reset/starfive,jhb100-crg.h | 25 ++++++++
3 files changed, 122 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml
new file mode 100644
index 000000000000..25ffb9d8dfcd
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jhb100-sys2crg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 System-2 Clock and Reset Generator
+
+maintainers:
+ - Changhuang Liang <changhuang.liang at starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jhb100-sys2crg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main Oscillator (25 MHz)
+ - description: PLL1
+ - description: GPU0 Non Coherent NOC Initiator
+ - description: GPU1 Non Coherent NOC Initiator
+
+ clock-names:
+ items:
+ - const: osc
+ - const: pll1
+ - const: gpu0_ncnoc_init
+ - const: gpu1_ncnoc_init
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive-jhb100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller at 13008000 {
+ compatible = "starfive,jhb100-sys2crg";
+ reg = <0x13008000 0x4000>;
+ clocks = <&osc>, <&pll1>, <&sys0crg 73>,
+ <&sys0crg 74>;
+ clock-names = "osc", "pll1", "gpu0_ncnoc_init",
+ "gpu1_ncnoc_init";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index d7904b32bd51..d19618e2a846 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -73,4 +73,37 @@
#define JHB100_SYS1CLK_BMCPER3_NCNOC_TARG 18
#define JHB100_SYS1CLK_BMCPER3_CFG_125 19
+/* SYS2CRG clocks */
+#define JHB100_SYS2CLK_JTAGM0_HCLK 3
+#define JHB100_SYS2CLK_JTAGM1_HCLK 4
+#define JHB100_SYS2CLK_JTAGM0_ATPG 5
+#define JHB100_SYS2CLK_JTAGM1_ATPG 6
+#define JHB100_SYS2CLK_JTAGM0_ATPG_TCLOCK 7
+#define JHB100_SYS2CLK_JTAGM1_ATPG_TCLOCK 8
+#define JHB100_SYS2CLK_JTAG0_MST_WRAP_HCLK 9
+#define JHB100_SYS2CLK_JTAG0_MST_WRAP_CLK_JTAG 10
+#define JHB100_SYS2CLK_JTAG0_MST_WRAP_APB_PCLK 11
+#define JHB100_SYS2CLK_JTAG0_MST_WRAP_ATPG_TCLOCK 12
+#define JHB100_SYS2CLK_JTAG1_MST_WRAP_HCLK 13
+#define JHB100_SYS2CLK_JTAG1_MST_WRAP_CLK_JTAG 14
+#define JHB100_SYS2CLK_JTAG1_MST_WRAP_APB_PCLK 15
+#define JHB100_SYS2CLK_JTAG1_MST_WRAP_ATPG_TCLOCK 16
+#define JHB100_SYS2CLK_HOSTUSB_NCNOC_TARG 17
+#define JHB100_SYS2CLK_HOSTUSBCMN_CFG_500 18
+#define JHB100_SYS2CLK_BMCPER1_NCNOC_TARG 19
+#define JHB100_SYS2CLK_BMCPER1_CFG_250 20
+#define JHB100_SYS2CLK_BMCPER1_CFG_143_DFT 21
+#define JHB100_SYS2CLK_BMCPER1_CFG_143 22
+#define JHB100_SYS2CLK_BMCPER0_NCNOC_TARG 23
+#define JHB100_SYS2CLK_GPU0_NCNOC_TARG 24
+#define JHB100_SYS2CLK_GPU0_BUS_CLK 25
+#define JHB100_SYS2CLK_GPU0_APB_CLK 26
+#define JHB100_SYS2CLK_GPU0_OSC_CLK 27
+#define JHB100_SYS2CLK_GPU1_NCNOC_TARG 28
+#define JHB100_SYS2CLK_GPU1_BUS_CLK 29
+#define JHB100_SYS2CLK_GPU1_APB_CLK 30
+#define JHB100_SYS2CLK_GPU1_OSC_CLK 31
+#define JHB100_SYS2CLK_MAIN_ICG_EN_JTAG0 32
+#define JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1 33
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h
index da1b51621172..fbc55f95e76c 100644
--- a/include/dt-bindings/reset/starfive,jhb100-crg.h
+++ b/include/dt-bindings/reset/starfive,jhb100-crg.h
@@ -36,4 +36,29 @@
#define JHB100_SYS1RST_BMCPERIPH3_RSTN_CRG 7
#define JHB100_SYS1RST_BMCPERIPH3_RSTN_BUS 8
+/* SYS2CRG resets */
+#define JHB100_SYS2RST_JTAG0_MST_WRAP_HRESETN 0
+#define JHB100_SYS2RST_JTAG0_MST_WRAP_APB_PRESETN 1
+#define JHB100_SYS2RST_JTAG1_MST_WRAP_HRESETN 2
+#define JHB100_SYS2RST_JTAG1_MST_WRAP_APB_PRESETN 3
+#define JHB100_SYS2RST_HUSBCMN_HOSTCMN_RSTN_BUS_NCNOC_INIT 4
+#define JHB100_SYS2RST_HUSBCMN_RSTN_HOSTCMN_CRG 5
+#define JHB100_SYS2RST_HUSBCMN_HOSTUSB0_RSTN_BUS_NCNOC_BMC_TARG 6
+#define JHB100_SYS2RST_HUSBCMN_HOSTUSB0_RSTN_BUS_NCNOC_HOST_TARG 7
+#define JHB100_SYS2RST_HUSBCMN_RSTN_BMC_CRG 8
+#define JHB100_SYS2RST_HUSBCMN_RSTN_HOSTUSB0_CRG 9
+#define JHB100_SYS2RST_HUSBCMN_HOSTUSB1_RSTN_BUS_NCNOC_BMC_TARG 10
+#define JHB100_SYS2RST_HUSBCMN_HOSTUSB1_RSTN_BUS_NCNOC_HOST_TARG 11
+#define JHB100_SYS2RST_HUSBCMN_RSTN_HOSTUSB1_CRG 12
+#define JHB100_SYS2RST_BMCPERIPH1_RSTN_CRG 13
+#define JHB100_SYS2RST_BMCPERIPH1_RSTN_BUS 14
+#define JHB100_SYS2RST_BMCPERIPH0_RSTN_CRG 15
+#define JHB100_SYS2RST_BMCPERIPH0_RSTN_BUS 16
+#define JHB100_SYS2RST_GPU0_RSTN_CRG 17
+#define JHB100_SYS2RST_GPU0_RSTN_BUS 18
+#define JHB100_SYS2RST_GPU0_HOST_PCIE_RST_N 19
+#define JHB100_SYS2RST_GPU1_RSTN_CRG 20
+#define JHB100_SYS2RST_GPU1_RSTN_BUS 21
+#define JHB100_SYS2RST_GPU1_HOST_PCIE_RST_N 22
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */
--
2.25.1
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