[PATCH v2 10/22] clk: starfive: Add JHB100 System-2 clock generator driver
Changhuang Liang
changhuang.liang at starfivetech.com
Thu May 7 22:36:20 PDT 2026
Add support for JHB100 System-2 clock generator (SYS2CRG).
Signed-off-by: Changhuang Liang <changhuang.liang at starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 ++
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-sys2.c | 128 ++++++++++++++++++
3 files changed, 137 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys2.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index b6042bcb5992..729bdfce7b8a 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -91,3 +91,11 @@ config CLK_STARFIVE_JHB100_SYS1
help
Say yes here to support the system-1 clock controller on the
StarFive JHB100 SoC.
+
+config CLK_STARFIVE_JHB100_SYS2
+ bool "StarFive JHB100 system-2 clock support"
+ depends on CLK_STARFIVE_JHB100_SYS0
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the system-2 clock controller on the
+ StarFive JHB100 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index b3571e2f0555..90b6390296bd 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys2.c b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c
new file mode 100644
index 000000000000..20ea5acf31ca
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 System-2 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang at starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-common.h"
+
+#define JHB100_SYS2CLK_NUM_CLKS (JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1 + 1)
+
+/* external clocks */
+#define JHB100_SYS2CLK_OSC (JHB100_SYS2CLK_NUM_CLKS + 0)
+#define JHB100_SYS2CLK_PLL1 (JHB100_SYS2CLK_NUM_CLKS + 1)
+#define JHB100_SYS2CLK_GPU0_NCNOC_INIT (JHB100_SYS2CLK_NUM_CLKS + 2)
+#define JHB100_SYS2CLK_GPU1_NCNOC_INIT (JHB100_SYS2CLK_NUM_CLKS + 3)
+
+char *jhb100_sys2_ext_clk[] = {
+ "osc",
+ "pll1",
+ "gpu0_ncnoc_init",
+ "gpu1_ncnoc_init",
+};
+
+static const struct starfive_clk_data jhb100_sys2crg_clk_data[] __initconst = {
+ /* jtag mst*/
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM0_HCLK, "jtagm0_hclk", 6,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM1_HCLK, "jtagm1_hclk", 6,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM0_ATPG, "jtagm0_ATPG", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM1_ATPG, "jtagm1_ATPG", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM0_ATPG_TCLOCK, "jtagm0_atpg_tclock", 2,
+ JHB100_SYS2CLK_JTAGM0_ATPG),
+ STARFIVE__DIV(JHB100_SYS2CLK_JTAGM1_ATPG_TCLOCK, "jtagm1_atpg_tclock", 2,
+ JHB100_SYS2CLK_JTAGM1_ATPG),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_HCLK, "jtag0_mst_wrap_hclk",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_HCLK),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_CLK_JTAG, "jtag0_mst_wrap_clk_jtag",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_HCLK),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_APB_PCLK, "jtag0_mst_wrap_apb_pclk",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_ATPG),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_ATPG_TCLOCK, "jtag0_mst_wrap_atpg_tclock",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_ATPG),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_HCLK, "jtag1_mst_wrap_hclk",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_HCLK),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_CLK_JTAG, "jtag1_mst_wrap_clk_jtag",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_HCLK),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_APB_PCLK, "jtag1_mst_wrap_apb_pclk",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_ATPG),
+ STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_ATPG_TCLOCK, "jtag1_mst_wrap_atpg_tclock",
+ CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_ATPG),
+ /* hostusbcmn */
+ STARFIVE__DIV(JHB100_SYS2CLK_HOSTUSB_NCNOC_TARG, "hostusb_ncnoc_targ", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_HOSTUSBCMN_CFG_500, "hostusbcmn_cfg_500", 4,
+ JHB100_SYS2CLK_PLL1),
+ /* bmcperiph1 */
+ STARFIVE__DIV(JHB100_SYS2CLK_BMCPER1_NCNOC_TARG, "bmcper1_ncnoc_targ", 6,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_BMCPER1_CFG_250, "bmcper1_cfg_250", 5,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE__DIV(JHB100_SYS2CLK_BMCPER1_CFG_143_DFT, "bmcper1_cfg_143_dft", 8,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE_GATE(JHB100_SYS2CLK_BMCPER1_CFG_143, "bmcper1_cfg_143", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_BMCPER1_CFG_143_DFT),
+ /* bmcperiph0 */
+ STARFIVE__DIV(JHB100_SYS2CLK_BMCPER0_NCNOC_TARG, "bmcper0_ncnoc_targ", 6,
+ JHB100_SYS2CLK_PLL1),
+ /* gpu0 */
+ STARFIVE__DIV(JHB100_SYS2CLK_GPU0_NCNOC_TARG, "gpu0_ncnoc_targ", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU0_BUS_CLK, "gpu0_bus_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_GPU0_NCNOC_INIT),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU0_APB_CLK, "gpu0_apb_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_GPU0_NCNOC_TARG),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU0_OSC_CLK, "gpu0_osc_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_OSC),
+ /* gpu1 */
+ STARFIVE__DIV(JHB100_SYS2CLK_GPU1_NCNOC_TARG, "gpu1_ncnoc_targ", 12,
+ JHB100_SYS2CLK_PLL1),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU1_BUS_CLK, "gpu1_bus_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_GPU1_NCNOC_INIT),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU1_APB_CLK, "gpu1_apb_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_GPU1_NCNOC_TARG),
+ STARFIVE_GATE(JHB100_SYS2CLK_GPU1_OSC_CLK, "gpu1_osc_clk", CLK_IS_CRITICAL,
+ JHB100_SYS2CLK_OSC),
+ /* main icg */
+ STARFIVE_GATE(JHB100_SYS2CLK_MAIN_ICG_EN_JTAG0, "main_icg_en_jtag0", 0,
+ JHB100_SYS2CLK_JTAGM0_HCLK),
+ STARFIVE_GATE(JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1, "main_icg_en_jtag1", 0,
+ JHB100_SYS2CLK_JTAGM1_HCLK),
+};
+
+const struct jhb100_crg_domain_info jhb100_sys2crg_info = {
+ .clk_data = jhb100_sys2crg_clk_data,
+ .num_clk = ARRAY_SIZE(jhb100_sys2crg_clk_data),
+ .ext_clk = jhb100_sys2_ext_clk,
+ .num_ext_clk = ARRAY_SIZE(jhb100_sys2_ext_clk),
+ .rst_name = "jhb100-r-sys2",
+ .power_domain = false,
+};
+
+static const struct of_device_id jhb100_sys2crg_match[] = {
+ {
+ .compatible = "starfive,jhb100-sys2crg",
+ .data = &jhb100_sys2crg_info,
+ },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jhb100_sys2crg_driver = {
+ .driver = {
+ .name = "clk-starfive-jhb100-sys2",
+ .of_match_table = jhb100_sys2crg_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(jhb100_sys2crg_driver, starfive_crg_probe);
--
2.25.1
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