[PATCH v2 4/4] riscv: dts: starfive: jhb100: Add JHB100 base DT

[Changhuang Liang]

Hi, Conor

Thanks for the review.

> On Wed, May 06, 2026 at 01:59:37AM -0700, Changhuang Liang wrote:
> > From: Ley Foon Tan <leyfoon.tan at starfivetech.com>
> >
> > Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT,
> > PLIC, PMU, UART, INTC and 1GB DDR.
> >
> > Signed-off-by: Ley Foon Tan <leyfoon.tan at starfivetech.com>
> > Signed-off-by: Changhuang Liang <changhuang.liang at starfivetech.com>

[...]

> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu0: cpu at 0 {
> > +			compatible = "starfive,dubhe-70", "riscv";
> > +			reg = <0x0>;
> 
> > +			riscv,isa = "rv64imafdcbh";
> 
> Please just remove this property.
> 
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba",
> "zbb",
> > +					       "zbc", "zbs", "zicbom", "zicbop", "zicboz",
> "zicntr",
> > +					       "zicond", "zicsr", "zifencei", "zihintpause",
> > +					       "zihpm", "svinval", "svnapot", "sscofpmf";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			d-cache-block-size = <64>;
> > +			d-cache-sets = <512>;
> > +			d-cache-size = <32768>;
> > +			d-tlb-sets = <1>;
> > +			d-tlb-size = <16>;
> > +			device_type = "cpu";
> > +			i-cache-block-size = <64>;
> > +			i-cache-sets = <512>;
> > +			i-cache-size = <32768>;
> > +			i-tlb-sets = <1>;
> > +			i-tlb-size = <24>;
> > +			mmu-type = "riscv,sv48";
> > +			next-level-cache = <&l2c0>;
> > +			tlb-split;
> > +
> > +			cpu0_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> 
> > +		cpu-map {
> > +			cluster0 {
> > +				core0 {
> > +					cpu = <&cpu0>;
> > +				};
> > +			};
> 
> Each cpu is in a different cluster? Interesting, suppose it makes sense when
> you have different l2 caches. What other resources are not shared?
> Do they have different cpu clocks too etc?

There are no other shared resources, except for the L3 cache.

> 
> > +
> > +			cluster1 {
> > +				core0 {
> > +					cpu = <&cpu1>;
> > +				};
> > +			};
> > +
> > +			cluster2 {
> > +				core0 {
> > +					cpu = <&cpu2>;
> > +				};
> > +			};
> > +
> > +			cluster3 {
> > +				core0 {
> > +					cpu = <&cpu3>;
> > +				};
> > +			};
> > +		};
> > +
> > +		l2c0: cache-controller-0 {
> > +			compatible = "cache";
> > +			cache-block-size = <64>;
> > +			cache-level = <2>;
> > +			cache-sets = <2048>;
> > +			cache-size = <0x20000>;
> > +			cache-unified;
> > +			next-level-cache = <&l3_cache>;
> > +		};
> > +
> > +		l2c1: cache-controller-1 {
> > +			compatible = "cache";
> > +			cache-block-size = <64>;
> > +			cache-level = <2>;
> > +			cache-sets = <2048>;
> > +			cache-size = <0x20000>;
> > +			cache-unified;
> > +			next-level-cache = <&l3_cache>;
> > +		};
> > +
> > +		l2c2: cache-controller-2 {
> > +			compatible = "cache";
> > +			cache-block-size = <64>;
> > +			cache-level = <2>;
> > +			cache-sets = <2048>;
> > +			cache-size = <0x20000>;
> > +			cache-unified;
> > +			next-level-cache = <&l3_cache>;
> > +		};
> > +
> > +		l2c3: cache-controller-3 {
> > +			compatible = "cache";
> > +			cache-block-size = <64>;
> > +			cache-level = <2>;
> > +			cache-sets = <2048>;
> > +			cache-size = <0x20000>;
> > +			cache-unified;
> > +			next-level-cache = <&l3_cache>;
> > +		};
> > +
> > +		l3_cache: cache-controller-4 {
> > +			compatible = "cache";
> > +			cache-block-size = <64>;
> > +			cache-level = <3>;
> > +			cache-sets = <1024>;
> > +			cache-size = <0x20000>;
> > +			cache-unified;
> > +		};
> > +	};
> 
> > +	clk_uart: clock-25000000 {
> > +		compatible = "fixed-clock"; /* Initial clock handler for UART */
> 
> What does this comment mean?

Here it's just a temporary clock; it will be replaced by the clock driver later.

Best Regards,
Changhuang