[PATCH v4 2/3] riscv: track effective hardware PTE A/D updating
Yunhui Cui
cuiyunhui at bytedance.com
Wed Jun 17 23:44:05 PDT 2026
Svadu being present in the ISA does not always mean that hardware PTE A/D
updating is active. When Svade and Svadu are both advertised, Svadu starts
disabled and must be enabled through SBI FWFT before the kernel can rely on
hardware A/D updates.
Track that effective runtime state with a static key. During init, enable
FWFT for all online harts before setting the key; if that fails, leave the
system in software-managed A/D mode. Secondary harts must match the global
A/D update mode before they are marked online.
The full state flow is:
boot init
|
v
do all CPUs have Svadu?
|
+------+------+
| |
no yes
| |
v v
hw_ad key = false does any CPU have Svade?
requires_fwft = false |
| +-----+-----+
| | |
| no yes
| | |
| v v
| hw_ad key = true requires_fwft = true
| requires_fwft = false |
| v
| FWFT on online CPUs
| |
| +------+------+
| | |
| success failure
| | |
| v v
| hw_ad key = true requires_fwft = false
| requires_fwft = true hw_ad key = false
| fallback to software A/D
|
+--------------+-----------+
|
v
hotplug CPU
|
v
if (!hw_ad_key || !requires_fwft)
|
+------+------+
| |
true false
| |
v v
return 0 enable local FWFT
| |
| +-----+-----+
| | |
| success failure
| | |
v v v
continue continue return error
| | |
v v v
set_cpu_online() do not set CPU online
| |
v v
CPU online CPU bringup fails
Thus, an online CPU never runs with an A/D update mode different from the
global kernel state.
Signed-off-by: Yunhui Cui <cuiyunhui at bytedance.com>
Reviewed-by: Qingwei Hu <qingwei.hu at bytedance.com>
---
arch/riscv/include/asm/cpufeature.h | 8 +++
arch/riscv/kernel/cpufeature.c | 101 ++++++++++++++++++++++++++--
arch/riscv/kernel/smpboot.c | 4 ++
3 files changed, 107 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 739fcc84bf7b2..ba3d74f6006a6 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -128,6 +128,14 @@ struct riscv_isa_ext_data {
extern const struct riscv_isa_ext_data riscv_isa_ext[];
extern const size_t riscv_isa_ext_count;
extern bool riscv_isa_fallback;
+DECLARE_STATIC_KEY_FALSE(riscv_hw_pte_ad_updating);
+
+static __always_inline bool riscv_has_hw_pte_ad_updating(void)
+{
+ return static_branch_unlikely(&riscv_hw_pte_ad_updating);
+}
+
+int riscv_enable_hw_pte_ad_updating(void);
unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index f46aa5602d74d..c0ac7ab39d4e0 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -15,6 +15,7 @@
#include <linux/memory.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/smp.h>
#include <asm/acpi.h>
#include <asm/alternative.h>
#include <asm/bugs.h>
@@ -35,6 +36,9 @@
static bool any_cpu_has_zicboz;
static bool any_cpu_has_zicbop;
static bool any_cpu_has_zicbom;
+DEFINE_STATIC_KEY_FALSE(riscv_hw_pte_ad_updating);
+EXPORT_SYMBOL_GPL(riscv_hw_pte_ad_updating);
+static bool riscv_hw_pte_ad_updating_requires_fwft __read_mostly;
unsigned long elf_hwcap __read_mostly;
@@ -287,15 +291,100 @@ static int riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data *data,
return -EPROBE_DEFER;
}
-static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data,
- const unsigned long *isa_bitmap)
+static void riscv_set_hw_pte_ad_updating(void)
+{
+ static_branch_enable(&riscv_hw_pte_ad_updating);
+}
+
+static int riscv_enable_local_hw_pte_ad_updating(void)
{
- /* SVADE has already been detected, use SVADE only */
- if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SVADE))
- return -EOPNOTSUPP;
+ return sbi_fwft_set(SBI_FWFT_PTE_AD_HW_UPDATING, 1, 0);
+}
+
+static int riscv_set_online_hw_pte_ad_updating(bool enable)
+{
+ return sbi_fwft_set_online_cpus(SBI_FWFT_PTE_AD_HW_UPDATING,
+ enable, 0);
+}
+
+static bool __init riscv_any_cpu_has_svade(void)
+{
+ unsigned int cpu;
+ for_each_possible_cpu(cpu) {
+ if (riscv_cpu_has_extension_unlikely(cpu, RISCV_ISA_EXT_SVADE))
+ return true;
+ }
+
+ return false;
+}
+
+int riscv_enable_hw_pte_ad_updating(void)
+{
+ unsigned int cpu;
+ int ret;
+
+ if (!riscv_has_hw_pte_ad_updating() ||
+ !riscv_hw_pte_ad_updating_requires_fwft)
+ return 0;
+
+ cpu = smp_processor_id();
+ ret = riscv_enable_local_hw_pte_ad_updating();
+ if (ret)
+ pr_err("CPU%u failed to enable hardware PTE A/D updating: %d\n",
+ cpu, ret);
+
+ return ret;
+}
+
+static void __init riscv_disable_hw_pte_ad_updating(int error)
+{
+ int ret;
+
+ riscv_hw_pte_ad_updating_requires_fwft = false;
+ if (error != -EOPNOTSUPP)
+ pr_err("Failed to enable hardware PTE A/D updating: %d\n",
+ error);
+
+ ret = riscv_set_online_hw_pte_ad_updating(false);
+ if (ret && ret != -EOPNOTSUPP)
+ pr_err("Failed to rollback hardware PTE A/D updating: %d\n",
+ ret);
+
+ pr_info("riscv: leave PTE A/D updates software-managed (%d)\n",
+ error);
+}
+
+static int __init riscv_hw_pte_ad_updating_init(void)
+{
+ bool requires_fwft, has_svadu;
+ int ret;
+
+ has_svadu = riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);
+ requires_fwft = riscv_any_cpu_has_svade();
+
+ if (!has_svadu)
+ return 0;
+
+ if (requires_fwft) {
+ riscv_hw_pte_ad_updating_requires_fwft = true;
+ ret = riscv_set_online_hw_pte_ad_updating(true);
+ if (ret) {
+ riscv_disable_hw_pte_ad_updating(ret);
+ return 0;
+ }
+ }
+
+ /*
+ * At this point hardware PTE A/D updating is active for all online
+ * harts, either from boot or from the FWFT setup above. Later harts
+ * must do the same in secondary startup before they are marked online.
+ */
+ riscv_set_hw_pte_ad_updating();
+ pr_debug("riscv: hardware PTE A/D updating enabled\n");
return 0;
}
+arch_initcall(riscv_hw_pte_ad_updating_init);
static int riscv_cfilp_validate(const struct riscv_isa_ext_data *data,
const unsigned long *isa_bitmap)
@@ -584,7 +673,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
__RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
- __RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),
+ __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU),
__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 8b628580fe118..4fe62f96bcca2 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -27,6 +27,7 @@
#include <linux/sched/mm.h>
#include <asm/cacheflush.h>
+#include <asm/cpufeature.h>
#include <asm/cpu_ops.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
@@ -221,6 +222,9 @@ asmlinkage __visible void smp_callin(void)
struct mm_struct *mm = &init_mm;
unsigned int curr_cpuid = smp_processor_id();
+ if (riscv_enable_hw_pte_ad_updating())
+ return;
+
if (has_vector()) {
/*
* Return as early as possible so the hart with a mismatching
--
2.39.5
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