[PATCH v1] iommu/riscv: Support 32-bit register accesses

[David Laight]

On Mon, 15 Jun 2026 12:38:17 +0000
Guo Ren <guoren at kernel.org> wrote:

> Hi Zhanpeng Zhang,
..
> 3. Only performance-monitoring counters require 64-bit IO access or the
> high-low-high do-while retry strategy. For ordinary status and control
> MMIO registers, a single read is sufficient.

Actually this sequence should be enough for a counter:
	hi = read_hi();
	lo = read_lo();
	if (hi != read_hi()) {
		// Pick a value that happened while doing the reads.
		hi++;
		lo = 0;
	}

-- David