[External] Re: [PATCH v1] iommu/riscv: Support 32-bit register accesses

[Zhanpeng Zhang]

Hi Andreas,

For a generic kernel, the expected setting is to leave
RISCV_IOMMU_32BIT_ACCESS disabled.

If supporting such platforms from a single generic kernel is preferred, I can
look into replacing this build-time option with a runtime indication.

Regards,
Zhanpeng

> From: "Andreas Schwab"<schwab at suse.de>
> Date:  Mon, Jun 15, 2026, 16:22
> Subject:  [External] Re: [PATCH v1] iommu/riscv: Support 32-bit register accesses
> To: "Zhanpeng Zhang"<zhangzhanpeng.jasper at bytedance.com>
> Cc: "Tomasz Jeznach"<tjeznach at rivosinc.com>, "Joerg Roedel"<joro at 8bytes.org>, "Will Deacon"<will at kernel.org>, "Robin Murphy"<robin.murphy at arm.com>, "Paul Walmsley"<pjw at kernel.org>, "Palmer Dabbelt"<palmer at dabbelt.com>, "Albert Ou"<aou at eecs.berkeley.edu>, "Alexandre Ghiti"<alex at ghiti.fr>, <iommu at lists.linux.dev>, <linux-riscv at lists.infradead.org>, <linux-kernel at vger.kernel.org>, "Xu Lu"<luxu.kernel at bytedance.com>, <cuiyunhui at bytedance.com>, <yuanzhu at bytedance.com>
> On Jun 15 2026, Zhanpeng Zhang wrote:
>
> > +config RISCV_IOMMU_32BIT_ACCESS
> > +        bool "Use 32-bit accesses for RISC-V IOMMU registers"
> > +        depends on RISCV_IOMMU
> > +        help
> > +          Say Y when the RISC-V IOMMU MMIO window cannot be accessed
> > +          using naturally aligned 64-bit loads and stores.
> > +
> > +          When enabled, 64-bit IOMMU registers are accessed as paired
> > +          32-bit MMIO operations. This option does not describe an RV32
> > +          kernel or a 32-bit IOMMU architecture.
>
> What is the expected setting in a generic kernel?
>
> --
> Andreas Schwab, SUSE Labs, schwab at suse.de
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