[PATCH v1] riscv: kvm: Use endian-specific __lelong for NACL shared memory

[Anup Patel]

On Mon, Jun 8, 2026 at 9:22 PM Sean Chang <seanwascoding at gmail.com> wrote:
>
> When compiling with sparse enabled (C=2), bitwise type warnings are
> triggered in the RISC-V KVM implementation. This occurs because the
> user-space data unboxing macro '__get_user_asm' performs implicit
> casting on restricted types without forcing the compiler's compliance.
>
> Additionally, raw 'unsigned long *' pointers are used to access the
> SBI NACL shared memory, whereas the RISC-V SBI specification mandates
> that these structures must follow little-endian byte ordering.
>
> Fix these by:
> 1. Adding a '__force' cast to '__get_user_asm()' to safely suppress
>    implicit cast warnings during user-space data fetching.
> 2. Introducing the '__lelong' type macro, which dynamically resolves to
>    '__le32' or '__le64' depending on XLEN, and replacing 'unsigned long *'
>    with '__lelong *' to enforce proper compile-time endianness checks.
>
> Signed-off-by: Sean Chang <seanwascoding at gmail.com>

LGTM.

Reviewed-by: Anup Patel <anup at brainfault.org>

Queued this patch for Linux-7.2

Thanks,
Anup

> ---
>  arch/riscv/include/asm/kvm_nacl.h | 14 ++++++++------
>  arch/riscv/include/asm/uaccess.h  |  2 +-
>  arch/riscv/kvm/nacl.c             |  2 +-
>  3 files changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/include/asm/kvm_nacl.h b/arch/riscv/include/asm/kvm_nacl.h
> index 4124d5e06a0f..f45407bcaa26 100644
> --- a/arch/riscv/include/asm/kvm_nacl.h
> +++ b/arch/riscv/include/asm/kvm_nacl.h
> @@ -60,9 +60,11 @@ int kvm_riscv_nacl_init(void);
>  #ifdef CONFIG_32BIT
>  #define lelong_to_cpu(__x)     le32_to_cpu(__x)
>  #define cpu_to_lelong(__x)     cpu_to_le32(__x)
> +#define __lelong                __le32
>  #else
>  #define lelong_to_cpu(__x)     le64_to_cpu(__x)
>  #define cpu_to_lelong(__x)     cpu_to_le64(__x)
> +#define __lelong                __le64
>  #endif
>
>  #define nacl_shmem()                                                   \
> @@ -70,7 +72,7 @@ int kvm_riscv_nacl_init(void);
>
>  #define nacl_scratch_read_long(__shmem, __offset)                      \
>  ({                                                                     \
> -       unsigned long *__p = (__shmem) +                                \
> +       __lelong *__p = (__shmem) +                                     \
>                              SBI_NACL_SHMEM_SCRATCH_OFFSET +            \
>                              (__offset);                                \
>         lelong_to_cpu(*__p);                                            \
> @@ -78,7 +80,7 @@ int kvm_riscv_nacl_init(void);
>
>  #define nacl_scratch_write_long(__shmem, __offset, __val)              \
>  do {                                                                   \
> -       unsigned long *__p = (__shmem) +                                \
> +       __lelong *__p = (__shmem) +                                     \
>                              SBI_NACL_SHMEM_SCRATCH_OFFSET +            \
>                              (__offset);                                \
>         *__p = cpu_to_lelong(__val);                                    \
> @@ -87,7 +89,7 @@ do {                                                                  \
>  #define nacl_scratch_write_longs(__shmem, __offset, __array, __count)  \
>  do {                                                                   \
>         unsigned int __i;                                               \
> -       unsigned long *__p = (__shmem) +                                \
> +       __lelong *__p = (__shmem) +                                     \
>                              SBI_NACL_SHMEM_SCRATCH_OFFSET +            \
>                              (__offset);                                \
>         for (__i = 0; __i < (__count); __i++)                           \
> @@ -168,7 +170,7 @@ __kvm_riscv_nacl_hfence(__shmem,                                    \
>
>  #define nacl_csr_read(__shmem, __csr)                                  \
>  ({                                                                     \
> -       unsigned long *__a = (__shmem) + SBI_NACL_SHMEM_CSR_OFFSET;     \
> +       __lelong *__a = (__shmem) + SBI_NACL_SHMEM_CSR_OFFSET;          \
>         lelong_to_cpu(__a[SBI_NACL_SHMEM_CSR_INDEX(__csr)]);            \
>  })
>
> @@ -176,7 +178,7 @@ __kvm_riscv_nacl_hfence(__shmem,                                    \
>  do {                                                                   \
>         void *__s = (__shmem);                                          \
>         unsigned int __i = SBI_NACL_SHMEM_CSR_INDEX(__csr);             \
> -       unsigned long *__a = (__s) + SBI_NACL_SHMEM_CSR_OFFSET;         \
> +       __lelong *__a = (__s) + SBI_NACL_SHMEM_CSR_OFFSET;              \
>         u8 *__b = (__s) + SBI_NACL_SHMEM_DBITMAP_OFFSET;                \
>         __a[__i] = cpu_to_lelong(__val);                                \
>         __b[__i >> 3] |= 1U << (__i & 0x7);                             \
> @@ -186,7 +188,7 @@ do {                                                                        \
>  ({                                                                     \
>         void *__s = (__shmem);                                          \
>         unsigned int __i = SBI_NACL_SHMEM_CSR_INDEX(__csr);             \
> -       unsigned long *__a = (__s) + SBI_NACL_SHMEM_CSR_OFFSET;         \
> +       __lelong *__a = (__s) + SBI_NACL_SHMEM_CSR_OFFSET;              \
>         u8 *__b = (__s) + SBI_NACL_SHMEM_DBITMAP_OFFSET;                \
>         unsigned long __r = lelong_to_cpu(__a[__i]);                    \
>         __a[__i] = cpu_to_lelong(__val);                                \
> diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h
> index 11c9886c3b70..5d4ec15584cf 100644
> --- a/arch/riscv/include/asm/uaccess.h
> +++ b/arch/riscv/include/asm/uaccess.h
> @@ -112,7 +112,7 @@ do {                                                                \
>                 _ASM_EXTABLE_UACCESS_ERR(1b, %l2, %0)           \
>                 : "=&r" (__tmp)                                 \
>                 : "m" (*(ptr)) : : label);                      \
> -       (x) = (__typeof__(x))(unsigned long)__tmp;              \
> +       (x) = (__force __typeof__(x))(unsigned long)__tmp;      \
>  } while (0)
>  #else /* !CONFIG_CC_HAS_ASM_GOTO_OUTPUT */
>  #define __get_user_asm(insn, x, ptr, label)                    \
> diff --git a/arch/riscv/kvm/nacl.c b/arch/riscv/kvm/nacl.c
> index 08a95ad9ada2..6f9f8963e9dd 100644
> --- a/arch/riscv/kvm/nacl.c
> +++ b/arch/riscv/kvm/nacl.c
> @@ -20,7 +20,7 @@ void __kvm_riscv_nacl_hfence(void *shmem,
>                              unsigned long page_count)
>  {
>         int i, ent = -1, try_count = 5;
> -       unsigned long *entp;
> +       __lelong *entp;
>
>  again:
>         for (i = 0; i < SBI_NACL_SHMEM_HFENCE_ENTRY_MAX; i++) {
> --
> 2.43.0
>