[PATCH v4 01/16] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically
Guodong Xu
docular.xu at gmail.com
Thu Jun 11 13:12:38 PDT 2026
The multi-letter extension enum is documented as being sorted
alphanumerically (see the "multi-letter extensions, sorted
alphanumerically" comment), but several Z entries have drifted out of
order.
Reorder the affected entries so the multi-letter Z list is sorted
alphanumerically again.
Signed-off-by: Guodong Xu <docular.xu at gmail.com>
---
v4: New patch.
---
.../devicetree/bindings/riscv/extensions.yaml | 184 ++++++++++-----------
1 file changed, 92 insertions(+), 92 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 2b0a8a93bb214..5ffc40d599c02 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -457,6 +457,13 @@ properties:
merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
of zc.adoc to src tree.").
+ - const: zclsd
+ description:
+ The Zclsd extension implements the compressed (16-bit) version of the
+ Load/Store Pair for RV32. As with Zilsd, this extension was ratified
+ in commit f88abf1 ("Integrating load/store pair for RV32 with the
+ main manual") of riscv-isa-manual.
+
- const: zcmop
description:
The standard Zcmop extension version 1.0, as ratified in commit
@@ -487,6 +494,22 @@ properties:
in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
riscv-isa-manual.
+ - const: zicbom
+ description:
+ The standard Zicbom extension for base cache management operations as
+ ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+
+ - const: zicbop
+ description:
+ The standard Zicbop extension for cache-block prefetch instructions
+ as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
+ riscv-CMOs.
+
+ - const: zicboz
+ description:
+ The standard Zicboz extension for cache-block zeroing as ratified
+ in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+
- const: ziccamoa
description:
The standard Ziccamoa extension for main memory (cacheability and
@@ -514,6 +537,66 @@ properties:
guarantee on LR/SC sequences, as ratified in commit b1d806605f87
("Updated to ratified state.") of the riscv profiles specification.
+ - const: zicfilp
+ description: |
+ The standard Zicfilp extension for enforcing forward edge
+ control-flow integrity as ratified in commit 3f8e450 ("merge
+ pull request #227 from ved-rivos/0709") of riscv-cfi
+ github repo.
+
+ - const: zicfiss
+ description: |
+ The standard Zicfiss extension for enforcing backward edge
+ control-flow integrity as ratified in commit 3f8e450 ("merge
+ pull request #227 from ved-rivos/0709") of riscv-cfi
+ github repo.
+
+ - const: zicntr
+ description:
+ The standard Zicntr extension for base counters and timers, as
+ ratified in the 20191213 version of the unprivileged ISA
+ specification.
+
+ - const: zicond
+ description:
+ The standard Zicond extension for conditional arithmetic and
+ conditional-select/move operations as ratified in commit 95cf1f9
+ ("Add changes requested by Ved during signoff") of riscv-zicond.
+
+ - const: zicsr
+ description: |
+ The standard Zicsr extension for control and status register
+ instructions, as ratified in the 20191213 version of the
+ unprivileged ISA specification.
+
+ This does not include Chapter 10, "Counters", which documents
+ special case read-only CSRs, that were moved into the Zicntr and
+ Zihpm extensions after the ratification of the 20191213 version of
+ the unprivileged specification.
+
+ - const: zifencei
+ description:
+ The standard Zifencei extension for instruction-fetch fence, as
+ ratified in the 20191213 version of the unprivileged ISA
+ specification.
+
+ - const: zihintntl
+ description:
+ The standard Zihintntl extension for non-temporal locality hints, as
+ ratified in commit 0dc91f5 ("Zihintntl is ratified") of the
+ riscv-isa-manual.
+
+ - const: zihintpause
+ description:
+ The standard Zihintpause extension for pause hints, as ratified in
+ commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
+
+ - const: zihpm
+ description:
+ The standard Zihpm extension for hardware performance counters, as
+ ratified in the 20191213 version of the unprivileged ISA
+ specification.
+
- const: zilsd
description:
The standard Zilsd extension which provides support for aligned
@@ -521,12 +604,10 @@ properties:
encodings, as ratified in commit f88abf1 ("Integrating
load/store pair for RV32 with the main manual") of riscv-isa-manual.
- - const: zclsd
+ - const: zimop
description:
- The Zclsd extension implements the compressed (16-bit) version of the
- Load/Store Pair for RV32. As with Zilsd, this extension was ratified
- in commit f88abf1 ("Integrating load/store pair for RV32 with the
- main manual") of riscv-isa-manual.
+ The standard Zimop extension version 1.0, as ratified in commit
+ 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.
- const: zk
description:
@@ -590,87 +671,6 @@ properties:
in version 1.0 of RISC-V Cryptography Extensions Volume I
specification.
- - const: zicbom
- description:
- The standard Zicbom extension for base cache management operations as
- ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
-
- - const: zicbop
- description:
- The standard Zicbop extension for cache-block prefetch instructions
- as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
- riscv-CMOs.
-
- - const: zicboz
- description:
- The standard Zicboz extension for cache-block zeroing as ratified
- in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
-
- - const: zicfilp
- description: |
- The standard Zicfilp extension for enforcing forward edge
- control-flow integrity as ratified in commit 3f8e450 ("merge
- pull request #227 from ved-rivos/0709") of riscv-cfi
- github repo.
-
- - const: zicfiss
- description: |
- The standard Zicfiss extension for enforcing backward edge
- control-flow integrity as ratified in commit 3f8e450 ("merge
- pull request #227 from ved-rivos/0709") of riscv-cfi
- github repo.
-
- - const: zicntr
- description:
- The standard Zicntr extension for base counters and timers, as
- ratified in the 20191213 version of the unprivileged ISA
- specification.
-
- - const: zicond
- description:
- The standard Zicond extension for conditional arithmetic and
- conditional-select/move operations as ratified in commit 95cf1f9
- ("Add changes requested by Ved during signoff") of riscv-zicond.
-
- - const: zicsr
- description: |
- The standard Zicsr extension for control and status register
- instructions, as ratified in the 20191213 version of the
- unprivileged ISA specification.
-
- This does not include Chapter 10, "Counters", which documents
- special case read-only CSRs, that were moved into the Zicntr and
- Zihpm extensions after the ratification of the 20191213 version of
- the unprivileged specification.
-
- - const: zifencei
- description:
- The standard Zifencei extension for instruction-fetch fence, as
- ratified in the 20191213 version of the unprivileged ISA
- specification.
-
- - const: zihintpause
- description:
- The standard Zihintpause extension for pause hints, as ratified in
- commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
-
- - const: zihintntl
- description:
- The standard Zihintntl extension for non-temporal locality hints, as
- ratified in commit 0dc91f5 ("Zihintntl is ratified") of the
- riscv-isa-manual.
-
- - const: zihpm
- description:
- The standard Zihpm extension for hardware performance counters, as
- ratified in the 20191213 version of the unprivileged ISA
- specification.
-
- - const: zimop
- description:
- The standard Zimop extension version 1.0, as ratified in commit
- 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.
-
- const: ztso
description:
The standard Ztso extension for total store ordering, as ratified
@@ -809,18 +809,18 @@ properties:
instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
- - const: zvksh
- description: |
- The standard Zvksh extension for ShangMi suite: SM3 secure hash
- instructions, as ratified in commit 56ed795 ("Update
- riscv-crypto-spec-vector.adoc") of riscv-crypto.
-
- const: zvksg
description:
The standard Zvksg extension for ShangMi algorithm suite with GCM
instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
+ - const: zvksh
+ description: |
+ The standard Zvksh extension for ShangMi suite: SM3 secure hash
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
- const: zvkt
description:
The standard Zvkt extension for vector data-independent execution
--
2.43.0
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