[PATCH v8 1/3] dt-bindings: timer: mips,p8700-gcru

[Krzysztof Kozlowski]

On 11/06/2026 09:39, Aleksa Paunovic wrote:
> Hi Krzysztof,
> 
> 
> On 6/11/26 08:54, Krzysztof Kozlowski wrote:
>> On 11/06/2026 08:51, Krzysztof Kozlowski wrote:
>>> On 10/06/2026 10:22, Aleksa Paunovic via B4 Relay wrote:
>>>> From: Aleksa Paunovic <aleksa.paunovic at htecgroup.com>
>>>>
>>>> Add dt-bindings for the GCR.U memory mapped timer device for RISC-V
>>>> platforms. The GCR.U memory region contains shadow copies of the RISC-V
>>>> mtime register and the hrtime Global Configuration Register.
>>>>
>>>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic at htecgroup.com>
>>> You keep ignoring reviews you received (14th May!) and sending same mistake.
>>>
>>> Can you address the emails?
> I wasn't really sure what the etiquette was for replying to Sashiko reviews, so I decided to
> address the comments for other patches and send a v8 without replying.
> 
> As for this patch, the GCR.U itself does start at 0x7F000, but the first 
> actual register (mtime) is at 0x7F050 [1]. 
> I'm not seeing any warnings when running dt_binding_check.

It's still a warning which you can easily reproduce on W=1 on dts. You
CANNOT have mismatch. If block starts at 0x7f000, first register CANNOT
start at different address or it completely does not matter where the
register is. It's contradictory. The block start address defines
where... does it start.

Best regards,
Krzysztof