[PATCH v2 5/5] PCI: spacemit-k1: Add Spacemit K3 PCIe host controller support

Andy Shevchenko andriy.shevchenko at linux.intel.com
Tue Jun 9 07:49:23 PDT 2026


On Tue, Jun 09, 2026 at 07:48:12PM +0530, Manivannan Sadhasivam wrote:
> On Sun, May 17, 2026 at 09:48:40AM +0800, Inochi Amaoto wrote:
> > The PCIe controller on Spacemit K3 is almost a standard Synopsys
> > DesignWare PCIe IP with extra link and reset control. Unlike
> > the PCIe controller on K1, this controller supports external MSI
> > interrupt controller and can use multiple PHYs at the same time.
> > 
> > Add driver to support PCIe controller on Spacemit K3 PCIe.

...

> > +static int k3_pcie_enable_phy(struct k1_pcie *pcie)
> > +{
> > +	int i, ret;

No need to have i signed.

> > +
> > +	for (i = 0; i < pcie->phy_count; i++) {
> > +		ret = phy_init(pcie->phy[i]);
> > +		if (ret)
> > +			goto err_phy;
> > +	}
> > +
> > +	return 0;
> > +
> > +err_phy:
> > +	while (--i >= 0)

	while (i--)

is shorter form of the same.

> > +		phy_exit(pcie->phy[i]);
> > +

...

> > +	regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC,
> > +			PCIE_IGNORE_PERSTN | PCIE_PERSTN_OE | PCIE_PERSTN_OUT);
> > +	usleep_range(1000, 2000);

fsleep(1 * USEC_PER_MSEC)

> > +	regmap_clear_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, PCIE_PERSTN_OUT);
> > +
> > +	msleep(PCIE_T_PVPERL_MS);

...

> > +	int i;

Why is 'i' signed?

-- 
With Best Regards,
Andy Shevchenko





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