[PATCH v2 7/7] riscv: dts: tenstorrent: Add Atlantis platform
Joel Stanley
joel at jms.id.au
Thu Jun 4 07:39:53 PDT 2026
Add initial support for the Tenstorrent Atlantis platform, based on the
Atlantis SoC featuring 8x RVA23-compliant Tenstorrent Ascalon-XG cores.
The evb machine represents an internal bringup vehicle with just the
interrupt controllers and a UART. This will be replaced in time with a
full featured machine once details are available.
Co-developed-by: Drew Fustini <fustini at kernel.org>
Signed-off-by: Drew Fustini <fustini at kernel.org>
Signed-off-by: Joel Stanley <joel at jms.id.au>
---
v2:
- Update mtimer compatible
- Add Drew's co-developed-by
- Correct aplic num-sources count
---
arch/riscv/boot/dts/tenstorrent/Makefile | 1 +
.../boot/dts/tenstorrent/atlantis-evb.dts | 33 ++
.../boot/dts/tenstorrent/atlantis-soc.dtsi | 471 ++++++++++++++++++
3 files changed, 505 insertions(+)
create mode 100644 arch/riscv/boot/dts/tenstorrent/atlantis-evb.dts
create mode 100644 arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi
diff --git a/arch/riscv/boot/dts/tenstorrent/Makefile b/arch/riscv/boot/dts/tenstorrent/Makefile
index 2c81faaba462..92d8bb1a683f 100644
--- a/arch/riscv/boot/dts/tenstorrent/Makefile
+++ b/arch/riscv/boot/dts/tenstorrent/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_TENSTORRENT) += blackhole-card.dtb
+dtb-$(CONFIG_ARCH_TENSTORRENT) += atlantis-evb.dtb
diff --git a/arch/riscv/boot/dts/tenstorrent/atlantis-evb.dts b/arch/riscv/boot/dts/tenstorrent/atlantis-evb.dts
new file mode 100644
index 000000000000..06259cca8357
--- /dev/null
+++ b/arch/riscv/boot/dts/tenstorrent/atlantis-evb.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/dts-v1/;
+
+#include "atlantis-soc.dtsi"
+
+/ {
+ model = "Tenstorrent Atlantis development platform";
+ compatible = "tenstorrent,atlantis-evb", "tenstorrent,atlantis";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x00000000 0x0 0x80000000>,
+ <0x1 0x80000000 0x0 0x80000000>;
+ };
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon console=ttyS0";
+ stdout-path = "serial0";
+ };
+};
+
+&uart1 {
+ /delete-property/ clocks;
+ clock-frequency = <5000000>;
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi b/arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi
new file mode 100644
index 000000000000..2513f0dcc62e
--- /dev/null
+++ b/arch/riscv/boot/dts/tenstorrent/atlantis-soc.dtsi
@@ -0,0 +1,471 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h>
+
+/ {
+ model = "Tenstorrent Atlantis";
+ compatible = "tenstorrent,atlantis";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <1000000000>;
+
+ cpu0: cpu at 0 {
+ compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+ "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+ "zifencei", "zihintntl", "zihintpause", "zihpm",
+ "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+ "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+ "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+ "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+ "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+ "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+ "smrnmi", "smstateen", "ssaia", "ssccptr",
+ "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+ "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <128>;
+ d-cache-block-size = <64>;
+ d-cache-size = <0x40000>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv57";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu1: cpu at 1 {
+ compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+ device_type = "cpu";
+ reg = <1>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+ "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+ "zifencei", "zihintntl", "zihintpause", "zihpm",
+ "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+ "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+ "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+ "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+ "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+ "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+ "smrnmi", "smstateen", "ssaia", "ssccptr",
+ "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+ "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <128>;
+ d-cache-block-size = <64>;
+ d-cache-size = <0x40000>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv57";
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu2: cpu at 2 {
+ compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+ device_type = "cpu";
+ reg = <2>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+ "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+ "zifencei", "zihintntl", "zihintpause", "zihpm",
+ "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+ "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+ "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+ "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+ "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+ "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+ "smrnmi", "smstateen", "ssaia", "ssccptr",
+ "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+ "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <128>;
+ d-cache-block-size = <64>;
+ d-cache-size = <0x40000>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv57";
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu3: cpu at 3 {
+ compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+ device_type = "cpu";
+ reg = <3>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+ "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+ "zifencei", "zihintntl", "zihintpause", "zihpm",
+ "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+ "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+ "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+ "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+ "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+ "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+ "smrnmi", "smstateen", "ssaia", "ssccptr",
+ "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+ "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <128>;
+ d-cache-block-size = <64>;
+ d-cache-size = <0x40000>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv57";
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu4: cpu at 4 {
+ compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+ device_type = "cpu";
+ reg = <4>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+ "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+ "zifencei", "zihintntl", "zihintpause", "zihpm",
+ "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+ "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+ "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+ "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+ "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+ "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+ "smrnmi", "smstateen", "ssaia", "ssccptr",
+ "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+ "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <128>;
+ d-cache-block-size = <64>;
+ d-cache-size = <0x40000>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv57";
+
+ cpu4_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu5: cpu at 5 {
+ compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+ device_type = "cpu";
+ reg = <5>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+ "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+ "zifencei", "zihintntl", "zihintpause", "zihpm",
+ "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+ "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+ "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+ "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+ "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+ "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+ "smrnmi", "smstateen", "ssaia", "ssccptr",
+ "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+ "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <128>;
+ d-cache-block-size = <64>;
+ d-cache-size = <0x40000>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv57";
+
+ cpu5_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu6: cpu at 6 {
+ compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+ device_type = "cpu";
+ reg = <6>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+ "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+ "zifencei", "zihintntl", "zihintpause", "zihpm",
+ "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+ "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+ "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+ "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+ "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+ "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+ "smrnmi", "smstateen", "ssaia", "ssccptr",
+ "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+ "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <128>;
+ d-cache-block-size = <64>;
+ d-cache-size = <0x40000>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv57";
+
+ cpu6_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu7: cpu at 7 {
+ compatible = "tenstorrent,ascalon-xg", "tenstorrent,ascalon", "riscv";
+ device_type = "cpu";
+ reg = <7>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif",
+ "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr",
+ "zifencei", "zihintntl", "zihintpause", "zihpm",
+ "zimop", "za64rs", "zawrs", "zfa", "zfbfmin", "zfh",
+ "zfhmin", "zca", "zcb", "zcmop", "zba", "zbb",
+ "zbs", "zkr", "zkt", "zvbb", "zvbc", "zvfbfmin",
+ "zvfbfwma", "zvfh", "zvfhmin", "zvkt", "sha",
+ "shcounterenw", "shgatpa", "shtvala", "shvsatpa",
+ "shvstvala", "shvstvecd", "smaia", "smmpm", "smnpm",
+ "smrnmi", "smstateen", "ssaia", "ssccptr",
+ "sscofpmf", "sscounterenw", "ssnpm", "ssstateen",
+ "sstc", "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <128>;
+ d-cache-block-size = <64>;
+ d-cache-size = <0x40000>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv57";
+
+ cpu7_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <0xc00000>;
+ cache-sets = <512>;
+ cache-unified;
+ };
+ };
+
+ clocks {
+ osc_24m: clock-24m {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc_24m";
+ #clock-cells = <0>;
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&aplic_s>;
+ ranges;
+
+ imsic_m: interrupt-controller at a0000000 {
+ compatible = "tenstorrent,atlantis-imsics", "riscv,imsics";
+ riscv,num-ids = <255>;
+ riscv,guest-index-bits = <6>;
+ reg = <0x0 0xa0000000 0x0 0x200000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>,
+ <&cpu2_intc 11>, <&cpu3_intc 11>,
+ <&cpu4_intc 11>, <&cpu5_intc 11>,
+ <&cpu6_intc 11>, <&cpu7_intc 11>;
+ msi-controller;
+ #msi-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <0>;
+ };
+
+ mtimer: timer at a2180000 {
+ compatible = "tenstorrent,atlantis-aclint-mtimer", "riscv,aclint-mtimer";
+ interrupts-extended = <&cpu0_intc 7>, <&cpu1_intc 7>,
+ <&cpu2_intc 7>, <&cpu3_intc 7>,
+ <&cpu4_intc 7>, <&cpu5_intc 7>,
+ <&cpu6_intc 7>, <&cpu7_intc 7>;
+ reg = <0x0 0xa2180000 0x0 0x8000 0x0 0xa2188000 0x0 0x8000>;
+ };
+
+ imsic_s: interrupt-controller at a4000000 {
+ compatible = "tenstorrent,atlantis-imsics", "riscv,imsics";
+ riscv,num-ids = <255>;
+ riscv,guest-index-bits = <6>;
+ reg = <0x0 0xa4000000 0x0 0x200000>;
+ interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>,
+ <&cpu2_intc 9>, <&cpu3_intc 9>,
+ <&cpu4_intc 9>, <&cpu5_intc 9>,
+ <&cpu6_intc 9>, <&cpu7_intc 9>;
+ msi-controller;
+ #msi-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <0>;
+ };
+
+ aplic_m: interrupt-controller at cc000000 {
+ compatible = "tenstorrent,atlantis-aplic", "riscv,aplic";
+ msi-parent = <&imsic_m>;
+ riscv,delegation = <&aplic_s 1 96>;
+ riscv,children = <&aplic_s>;
+ reg = <0x0 0xcc000000 0x0 0x4000000>;
+ riscv,num-sources = <128>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ };
+
+ prcm_rcpu: clock-controller at d0000000 {
+ compatible = "tenstorrent,atlantis-prcm-rcpu";
+ reg = <0x00 0xd0000000 0x00 0x10000>;
+ clocks = <&osc_24m>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks = <&prcm_rcpu CLK_RCPU_ROOT>, <&prcm_rcpu CLK_NOCC_CLK>;
+ assigned-clock-parents = <&prcm_rcpu CLK_RCPU_ROOT>,
+ <&prcm_rcpu CLK_NOC_PLL>;
+ };
+
+ uart0: serial at d4100000 {
+ compatible = "snps,dw-apb-uart";
+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&prcm_rcpu CLK_UART0_PCLK>;
+ reg = <0x0 0xd4100000 0x0 0x10000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart1: serial at d4110000 {
+ compatible = "snps,dw-apb-uart";
+ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&prcm_rcpu CLK_UART1_PCLK>;
+ reg = <0x0 0xd4110000 0x0 0x10000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial at d4120000 {
+ compatible = "snps,dw-apb-uart";
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&prcm_rcpu CLK_UART2_PCLK>;
+ reg = <0x0 0xd4120000 0x0 0x10000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial at d4130000 {
+ compatible = "snps,dw-apb-uart";
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&prcm_rcpu CLK_UART3_PCLK>;
+ reg = <0x0 0xd4130000 0x0 0x10000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart4: serial at d4140000 {
+ compatible = "snps,dw-apb-uart";
+ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&prcm_rcpu CLK_UART4_PCLK>;
+ reg = <0x0 0xd4140000 0x0 0x10000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ aplic_s: interrupt-controller at e8000000 {
+ compatible = "tenstorrent,atlantis-aplic", "riscv,aplic";
+ msi-parent = <&imsic_s>;
+ riscv,num-sources = <128>;
+ reg = <0x0 0xe8000000 0x0 0x4000000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ };
+ };
+};
--
2.47.3
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