[PATCH v6 8/8] KVM: riscv: selftests: add Zicfiss/Zicfilp extension to get-reg-list test
Anup Patel
anup at brainfault.org
Wed Jul 29 06:10:46 PDT 2026
On Mon, Jul 13, 2026 at 6:34 AM Inochi Amaoto <inochiama at gmail.com> wrote:
>
> The KVM RISC-V allows Zicfiss/Zicfilp extensions for Guest/VM so
> add these extensions to get-reg-list test.
>
> Assisted-by: YuanSheng:claude-4.7-opus
> Co-developed-by: Quan Zhou <zhouquan at iscas.ac.cn>
> Signed-off-by: Quan Zhou <zhouquan at iscas.ac.cn>
> Signed-off-by: Inochi Amaoto <inochiama at gmail.com>
LGTM.
Reviewed-by: Anup Patel <anup at brainfault.org>
Thanks,
Anup
> ---
> .../selftests/kvm/riscv/get-reg-list.c | 69 +++++++++++++++++++
> 1 file changed, 69 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index 94e33b2ee796..bf3980e9db12 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -90,6 +90,8 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICFILP:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICFISS:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICOND:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICSR:
> @@ -358,6 +360,8 @@ static const char *core_id_to_str(const char *prefix, __u64 id)
> "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")"
> #define RISCV_CSR_SMSTATEEN(csr) \
> "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")"
> +#define RISCV_CSR_ZICFISS(csr) \
> + "KVM_REG_RISCV_CSR_ZICFISS | KVM_REG_RISCV_CSR_ZICFISS_REG(" #csr ")"
>
> static const char *general_csr_id_to_str(__u64 reg_off)
> {
> @@ -425,6 +429,18 @@ static const char *smstateen_csr_id_to_str(__u64 reg_off)
> return NULL;
> }
>
> +static const char *zicfiss_csr_id_to_str(__u64 reg_off)
> +{
> + /* reg_off is the offset into struct kvm_riscv_zicfiss_csr */
> + switch (reg_off) {
> + case KVM_REG_RISCV_CSR_ZICFISS_REG(ssp):
> + return RISCV_CSR_ZICFISS(ssp);
> + }
> +
> + TEST_FAIL("Unknown zicfiss csr reg: 0x%llx", reg_off);
> + return NULL;
> +}
> +
> static const char *csr_id_to_str(const char *prefix, __u64 id)
> {
> __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR);
> @@ -441,6 +457,8 @@ static const char *csr_id_to_str(const char *prefix, __u64 id)
> return aia_csr_id_to_str(reg_off);
> case KVM_REG_RISCV_CSR_SMSTATEEN:
> return smstateen_csr_id_to_str(reg_off);
> + case KVM_REG_RISCV_CSR_ZICFISS:
> + return zicfiss_csr_id_to_str(reg_off);
> }
>
> return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
> @@ -585,6 +603,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
> KVM_ISA_EXT_ARR(ZICBOP),
> KVM_ISA_EXT_ARR(ZICBOZ),
> KVM_ISA_EXT_ARR(ZICCRSE),
> + KVM_ISA_EXT_ARR(ZICFILP),
> + KVM_ISA_EXT_ARR(ZICFISS),
> KVM_ISA_EXT_ARR(ZICNTR),
> KVM_ISA_EXT_ARR(ZICOND),
> KVM_ISA_EXT_ARR(ZICSR),
> @@ -748,6 +768,12 @@ static const char *sbi_fwft_id_to_str(__u64 reg_off)
> case 6: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.enable)";
> case 7: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.flags)";
> case 8: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.value)";
> + case 9: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.enable)";
> + case 10: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.flags)";
> + case 11: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.value)";
> + case 12: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.enable)";
> + case 13: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.flags)";
> + case 14: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.value)";
> }
> return strdup_printf("KVM_REG_RISCV_SBI_FWFT | %lld /* UNKNOWN */", reg_off);
> }
> @@ -954,6 +980,20 @@ static __u64 sbi_fwft_pte_ad_hw_updating_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.value),
> };
>
> +static __u64 sbi_fwft_landing_pad_regs[] = {
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT,
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.enable),
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.flags),
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.value),
> +};
> +
> +static __u64 sbi_fwft_shadow_stack_regs[] = {
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT,
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.enable),
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.flags),
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.value),
> +};
> +
> static __u64 zicbom_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size),
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM,
> @@ -969,6 +1009,11 @@ static __u64 zicboz_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ,
> };
>
> +static __u64 zicfiss_regs[] = {
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_ZICFISS | KVM_REG_RISCV_CSR_ZICFISS_REG(ssp),
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICFISS,
> +};
> +
> static __u64 aia_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect),
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1),
> @@ -1220,6 +1265,8 @@ KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
> KVM_ISA_EXT_SUBLIST_CONFIG(zicbop, ZICBOP);
> KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);
> KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zicfilp, ZICFILP);
> +KVM_ISA_EXT_SUBLIST_CONFIG(zicfiss, ZICFISS);
> KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);
> KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND);
> KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR);
> @@ -1279,6 +1326,24 @@ static struct vcpu_reg_list config_sbi_fwft_pte_ad_hw_updating = {
> },
> };
>
> +static struct vcpu_reg_list config_sbi_fwft_landing_pad = {
> + .sublists = {
> + SUBLIST_BASE,
> + SUBLIST_ISA(zicfilp, ZICFILP),
> + SUBLIST_SBI(fwft_landing_pad, FWFT),
> + {0},
> + },
> +};
> +
> +static struct vcpu_reg_list config_sbi_fwft_shadow_stack = {
> + .sublists = {
> + SUBLIST_BASE,
> + SUBLIST_ISA(zicfiss, ZICFISS),
> + SUBLIST_SBI(fwft_shadow_stack, FWFT),
> + {0},
> + },
> +};
> +
> struct vcpu_reg_list *vcpu_configs[] = {
> &config_sbi_base,
> &config_sbi_sta,
> @@ -1289,6 +1354,8 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_sbi_fwft_misaligned_deleg,
> &config_sbi_fwft_pointer_masking,
> &config_sbi_fwft_pte_ad_hw_updating,
> + &config_sbi_fwft_landing_pad,
> + &config_sbi_fwft_shadow_stack,
> &config_aia,
> &config_fp_f,
> &config_fp_d,
> @@ -1332,6 +1399,8 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_zicbop,
> &config_zicboz,
> &config_ziccrse,
> + &config_zicfilp,
> + &config_zicfiss,
> &config_zicntr,
> &config_zicond,
> &config_zicsr,
> --
> 2.55.0
>
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