[PATCH v2 0/6] Add workarounds for Picoheart erratas
Yicong Yang
yang.yicong at picoheart.com
Tue Jul 28 02:46:21 PDT 2026
This series add basic errata framework for Picoheart SoCs for handling
upcoming Picoheart erratas. And add workarounds for the first two
erratas on our hardware. Also do some fixups and refactor in support
of the erratas.
Change since v1:
- factor out a common get_insn for reading userspace instructions
- fix the issue from reading instructions of a exec-only mapping
- cleanups and code style refinements per comments
Link: https://lore.kernel.org/linux-riscv/20260715084724.26578-1-yang.yicong@picoheart.com/
Yicong Yang (6):
riscv: Make get_insn public for instruction fault handling
riscv: insn: Set sstatus.MXR when reading userspace instruction
riscv: insn: Support decoding of CBO instructions
riscv: errata: Add init framework for picoheart errata
riscv: errata: picoheart: Add workaround for cbo.clean errata
riscv: errata: picoheart: Add workaround for AMOCASQ errata
arch/riscv/Kconfig.errata | 34 +++
arch/riscv/errata/Makefile | 1 +
arch/riscv/errata/picoheart/Makefile | 5 +
arch/riscv/errata/picoheart/errata.c | 238 +++++++++++++++++++
arch/riscv/include/asm/alternative.h | 3 +
arch/riscv/include/asm/cmpxchg.h | 2 +-
arch/riscv/include/asm/cpufeature.h | 8 +
arch/riscv/include/asm/csr.h | 1 +
arch/riscv/include/asm/errata_list.h | 25 +-
arch/riscv/include/asm/errata_list_vendors.h | 4 +
arch/riscv/include/asm/insn.h | 63 ++++-
arch/riscv/include/asm/processor.h | 2 +-
arch/riscv/include/asm/vendorid_list.h | 1 +
arch/riscv/kernel/alternative.c | 5 +
arch/riscv/kernel/asm-offsets.c | 6 +-
arch/riscv/kernel/cpufeature.c | 16 +-
arch/riscv/kernel/entry.S | 14 +-
arch/riscv/kernel/traps.c | 4 +
arch/riscv/kernel/traps_misaligned.c | 52 ----
arch/riscv/kernel/vector.c | 6 +-
20 files changed, 419 insertions(+), 71 deletions(-)
create mode 100644 arch/riscv/errata/picoheart/Makefile
create mode 100644 arch/riscv/errata/picoheart/errata.c
--
2.50.1 (Apple Git-155)
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