[PATCH v3 04/21] pinctrl: starfive: Add StarFive JHB100 sys0 controller driver

Changhuang Liang changhuang.liang at starfivetech.com
Sun Jul 26 20:26:04 PDT 2026


Hi, Linus

Thanks for the review.

> On Sat, Jul 25, 2026 at 12:25 PM Changhuang Liang
> <changhuang.liang at starfivetech.com> wrote:
> > > On Wed, Jun 3, 2026 at 7:54 AM Changhuang Liang
> > > <changhuang.liang at starfivetech.com> wrote:
> 
> > > > +static unsigned int jhb100_gpio_to_pin(struct gpio_chip *gc,
> > > > +unsigned int gpio) {
> > > > +       struct jhb100_gpio_bank *bank = jhb100_gc_to_bank(gc);
> > > > +
> > > > +       return bank->id * JHB100_NR_GPIOS_PER_BANK + gpio; }
> > >
> > > This usually tells me that GPIO_GENERIC can be used but maybe this
> > > has been discussed before...
> >
> > Here, the main purpose is to convert GPIOs into pins for configuring
> > certain pinctrl settings. I haven't found the part where GPIO_GENERIC can
> assist with this.
> > Can you point it out for me? Thank you very much.
> 
> Normally GPIO chips use the .config() callback when you want to set pin
> config for a certain pin in a pinctrl backend.
> 
> See Documentation/driver-api/gpio/driver.rst:
> 
> "The .set_config() callback uses the same enumerators and configuration
> semantics as the generic pin control drivers. This is not a coincidence: it is
> possible to assign the .set_config() to the function gpiochip_generic_config()
> which will result in pinctrl_gpio_set_config() being called and eventually
> ending up in the pin control back-end "behind" the GPIO controller, usually
> closer to the actual pins. This way the pin controller can manage the below
> listed GPIO configurations.
> 
> If a pin controller back-end is used, the GPIO controller or hardware
> description needs to provide "GPIO ranges" mapping the GPIO line offsets to
> pin numbers on the pin controller so they can properly cross-reference each
> other."
> 
> Maybe this is what you're looking for?

I will test this new method. It looks very meaningful. Thank you very much.

Best Regards,
Changhuang


More information about the linux-riscv mailing list