[PATCH] bpf, riscv: fix missing extable entry for arena load_acquire
Pu Lehui
pulehui at huawei.com
Thu Jul 16 00:01:21 PDT 2026
On 2026/7/16 14:15, Feng Jiang wrote:
> emit_atomic_ld_st() returns 1 to have build_body() skip the zext after
> a sub-word load_acquire. The caller does "ret = ret ?:
> add_exception_handler(...)", which skips add_exception_handler() on any
> non-zero ret, so the extable entry is missing and a faulting
> PROBE_ATOMIC load_acquire oopses.
>
> Check ret >= 0 before calling add_exception_handler(), and return ret
> unchanged so build_body() still skips the zext.
>
> Fixes: fb7cefabae81 ("riscv, bpf: Add support arena atomics for RV64")
> Signed-off-by: Feng Jiang <jiangfeng at kylinos.cn>
> ---
> arch/riscv/net/bpf_jit_comp64.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
> index f9d5347ba966..4fd4392dd080 100644
> --- a/arch/riscv/net/bpf_jit_comp64.c
> +++ b/arch/riscv/net/bpf_jit_comp64.c
> @@ -1986,10 +1986,14 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
> else
> ret = emit_atomic_rmw(rd, rs, insn, ctx);
>
> - ret = ret ?: add_exception_handler(insn, REG_DONT_CLEAR_MARKER, ctx);
> - if (ret)
> - return ret;
> - break;
> + /* ret can be 1 (skip-zext); extable entry still needs to be added */
> + if (ret >= 0) {
> + int err = add_exception_handler(insn, REG_DONT_CLEAR_MARKER, ctx);
Thanks Feng Jiang. Maybe we could remove this additional variable.
```
/* ret can be 1 (skip-zext); extable entry still needs to be added */
if (ret >= 0)
ret = add_exception_handler(insn, REG_DONT_CLEAR_MARKER, ctx) ?: ret;
if (ret)
return ret;
break;
```
> +
> + if (err)
> + return err;
> + }
> + return ret;
>
> default:
> pr_err("bpf-jit: unknown opcode %02x\n", code);
>
> ---
> base-commit: a13c140cc289c0b7b3770bce5b3ad42ab35074aa
> change-id: 20260716-bpf-riscv-fix-extable-399947ca778d
>
> Best regards,
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