[External] Re: [PATCH RESEND 1/2] riscv: mm: Apply svinval in update_mmu_cache()

[Xu Lu]

Hi Paul,

Yes, it makes more sense. Go ahead please.

Best regards.
Xu Lu

On Sat, Jul 11, 2026 at 8:04 AM Paul Walmsley <pjw at kernel.org> wrote:
>
> Hi,
>
> On Mon, 1 Sep 2025, Xu Lu wrote:
>
> > Only flush tlb of the specified mm, and apply svinval if available.
> >
> > Signed-off-by: Xu Lu <luxu.kernel at bytedance.com>
>
> I wound up splitting this into two separate patches, rather than one
> patch, since there seem to be two orthogonal changes.  The first change
> restricts the sfence.vma to a particular ASID (below).  The second change
> involves the Svinval path, and is sent in a subsequent message.
> What do you think?
>
>
> - Paul
>
>
> From: Xu Lu <luxu.kernel at bytedance.com>
> Date: Mon, 1 Sep 2025 19:41:40 +0800
> Subject: [PATCH 1/2] riscv: mm: flush TLB by ASID in update_mmu_cache_range()
>
> Only flush the TLB of the specified mm (via local_flush_tlb_page_asid)
>
> Signed-off-by: Xu Lu <luxu.kernel at bytedance.com>
> Link: https://patch.msgid.link/20250901114141.5438-2-luxu.kernel@bytedance.com
> [pjw at kernel.org: split the non-Svinval code in the original into this patch; update description]
> Signed-off-by: Paul Walmsley <pjw at kernel.org>
> ---
>  arch/riscv/include/asm/pgtable.h  | 7 +++++--
>  arch/riscv/include/asm/tlbflush.h | 5 +++++
>  arch/riscv/mm/tlbflush.c          | 5 -----
>  3 files changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 5d5756bda82e..755495a542cc 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -568,6 +568,8 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf,
>                 struct vm_area_struct *vma, unsigned long address,
>                 pte_t *ptep, unsigned int nr)
>  {
> +       unsigned long asid;
> +
>         /*
>          * Svvptc guarantees that the new valid pte will be visible within
>          * a bounded timeframe, so when the uarch does not cache invalid
> @@ -583,10 +585,11 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf,
>          * Relying on flush_tlb_fix_spurious_fault would suffice, but
>          * the extra traps reduce performance.  So, eagerly SFENCE.VMA.
>          */
> +       asid = get_mm_asid(vma->vm_mm);
>         while (nr--)
> -               local_flush_tlb_page(address + nr * PAGE_SIZE);
> -
> +               local_flush_tlb_page_asid(address + nr * PAGE_SIZE, asid);
>  }
> +
>  #define update_mmu_cache(vma, addr, ptep) \
>         update_mmu_cache_range(NULL, vma, addr, ptep, 1)
>
> diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
> index eed0abc40514..7c2cd5cc92d3 100644
> --- a/arch/riscv/include/asm/tlbflush.h
> +++ b/arch/riscv/include/asm/tlbflush.h
> @@ -15,6 +15,11 @@
>  #define FLUSH_TLB_NO_ASID       ((unsigned long)-1)
>
>  #ifdef CONFIG_MMU
> +static inline unsigned long get_mm_asid(struct mm_struct *mm)
> +{
> +       return mm ? cntx2asid(atomic_long_read(&mm->context.id)) : FLUSH_TLB_NO_ASID;
> +}
> +
>  static inline void local_flush_tlb_all(void)
>  {
>         __asm__ __volatile__ ("sfence.vma" : : : "memory");
> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index 8404530ec00f..73c226f719c7 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -110,11 +110,6 @@ static void __ipi_flush_tlb_range_asid(void *info)
>         local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid);
>  }
>
> -static inline unsigned long get_mm_asid(struct mm_struct *mm)
> -{
> -       return mm ? cntx2asid(atomic_long_read(&mm->context.id)) : FLUSH_TLB_NO_ASID;
> -}
> -
>  static void __flush_tlb_range(struct mm_struct *mm,
>                               const struct cpumask *cmask,
>                               unsigned long start, unsigned long size,
> --
> 2.53.0
>
>
>