[PATCH bpf-next v3 1/3] riscv, bpf: Add support for BPF_SDIV and BPF_SMOD in RV32 JIT

[bot+bpf-ci at kernel.org]

> commit c5a973b7fc82eeb9b84aaf80fc2673a94ab795b2
> Author: Kuan-Wei Chiu <visitorckw at gmail.com>
>
>     riscv, bpf: Add support for BPF_SDIV and BPF_SMOD in RV32 JIT
>
>     The current rv32 bpf jit compiler incorrectly treats BPF_SDIV and
>     BPF_SMOD as unsigned operations. The BPF instruction set allows
>     signed division and modulo by reusing the BPF_DIV and BPF_MOD opcodes
>     with the instruction offset set to 1.
>
>     Update the emit_alu_r32() function to accept an 'is_sdiv' variable and
>     emit the correct div and rem instructions when the offset is 1.
>
>     Before this patch:
>     [   44.161771] test_bpf: #165 ALU_SDIV_X: -6 / 2 = -3 jited:1 ret 2147483645 != -3 (0x7ffffffd != 0xfffffffd)FAIL (1 times)
>     [   44.167385] test_bpf: #166 ALU_SDIV_K: -6 / 2 = -3 jited:1 ret 2147483645 != -3 (0x7ffffffd != 0xfffffffd)FAIL (1 times)
>     [   44.171053] test_bpf: #169 ALU_SMOD_X: -7 % 2 = -1 jited:1 ret 1 != -1 (0x1 != 0xffffffff)FAIL (1 times)
>     [   44.172081] test_bpf: #170 ALU_SMOD_K: -7 % 2 = -1 jited:1 ret 1 != -1 (0x1 != 0xffffffff)FAIL (1 times)
>
>     After this patch:
>     [   16.002192] test_bpf: #165 ALU_SDIV_X: -6 / 2 = -3 jited:1 95 PASS
>     [   16.002983] test_bpf: #166 ALU_SDIV_K: -6 / 2 = -3 jited:1 1059 PASS
>     [   16.017167] test_bpf: #169 ALU_SMOD_X: -7 % 2 = -1 jited:1 136 PASS
>     [   16.023002] test_bpf: #170 ALU_SMOD_K: -7 % 2 = -1 jited:1 109 PASS
>
>     Signed-off-by: Kuan-Wei Chiu <visitorckw at gmail.com>

This looks like a bug fix for the original RV32 BPF JIT implementation.
Should this include:

  Fixes: 5f316b65e99f ("riscv, bpf: Add RV32G eBPF JIT")


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