[PATCH v1.1 4/7] dt-bindings: iommu: Add spacemit/t100 features
郑律
lv.zheng at spacemit.com
Thu Jan 29 02:43:03 PST 2026
> From: "Conor Dooley"<conor at kernel.org>
> Date: Thu, Jan 29, 2026, 18:08
> Subject: Re: [PATCH v1.1 4/7] dt-bindings: iommu: Add spacemit/t100 features
> To: "Lv Zheng"<lv.zheng at spacemit.com>
> Cc: "Tomasz Jeznach"<tjeznach at rivosinc.com>, "Joerg Roedel"<joro at 8bytes.org>, "Will Deacon"<will at kernel.org>, "Robin Murphy"<robin.murphy at arm.com>, "Rob Herring"<robh at kernel.org>, "Krzysztof Kozlowski"<krzk+dt at kernel.org>, "Conor Dooley"<conor+dt at kernel.org>, "Paul Walmsley"<pjw at kernel.org>, "Palmer Dabbelt"<palmer at dabbelt.com>, "Albert Ou"<aou at eecs.berkeley.edu>, "Alexandre Ghiti"<alex at ghiti.fr>, "Jingyu Li"<joey.li at spacemit.com>, "Zhijian Chen"<zhijian at spacemit.com>, <iommu at lists.linux.dev>, <linux-perf-users at vger.kernel.org>, <linux-riscv at lists.infradead.org>, <spacemit at lists.linux.dev>, <devicetree at vger.kernel.org>
> On Thu, Jan 29, 2026 at 02:09:13PM +0800, Lv Zheng wrote:
> > Adds device tree bindings for SpacemiT T100 specific features.
> >
> > vendor-hpm-events: Allow vendor events to be customized in the device
> > tree.
> > global-filter: The feature saves silicon area by reducing filters to
> > one and use it as a global filter across all events.
> > This usually is sufficient for real applications.
>
> Why can these not be determined from a device specific compatible?
The specification only defines less than 10 standard event types while the
real silicons should have implemented many other event types based on
their micro-architecture. I tried to provide a common mechanism for all
vendor specific event types across different vendors.
It is similar for the global filter, the global filter mechanism actually
complies to the IOMMU specification, users can alter the iohpmevt
registers as is what is specified in the IOMMU specification. It only
provides slight application difference between the final effection. Thus
this could also be a non-device specific option.
>
> > Signed-off-by: Lv Zheng <lv.zheng at spacemit.com>
> > Signed-off-by: Jingyu Li <joey.li at spacemit.com>
> > ---
> > .../bindings/iommu/riscv,iommu.yaml | 60 ++++++++++++++++++-
> > 1 file changed, 59 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> > index d4838c3b3741..0378eef1f34e 100644
> > --- a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> > +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> > @@ -57,17 +57,42 @@ properties:
> >
> > interrupts:
> > minItems: 1
> > - maxItems: 4
> > + maxItems: 68
> > description:
> > Wired interrupt vectors available for RISC-V IOMMU to notify the
> > RISC-V HARTS. The cause to interrupt vector is software defined
> > using IVEC IOMMU register.
> > + Normally the number of interrupt vectors available is 4 for IOATS
> > + civ/fiv/pmiv/piv interrupts. But for SpacemiT distributed IOMMU,
> > + the number of interrupt vectors includes IOATC pmiv wired
> > + interrupts and the maximum number of IOATCs can be up to 64.
>
> The extension to 68 should only be permitted for a soc-specific
> compatible.
Sure.
>
> > +
> > + interrupt-names:
> > + minItems: 1
> > + maxItems: 68
> >
> > msi-parent: true
> >
> > power-domains:
> > maxItems: 1
> >
> > + vendor-hpm-events:
> > + minItems: 1
> > + maxItems: 120
> > + description:
> > + Each item defines a vendor specific event using the format of
> > + "eventId[:eventName]", where the eventId is an integer filling the
> > + eventID field of the iohpmevt register and the eventName is an
> > + optional string used as the annotation of the event instead of the
> > + default name "eventId".
> > + $ref: /schemas/types.yaml#/definitions/string-array
> > +
> > + global-filter:
> > + type: boolean
> > + description:
> > + Indicate the filters programmed across iohpmevt registers are wired
> > + together in hardware as a global filter applied to all HPM events.
> > +
> > required:
> > - compatible
> > - reg
> > @@ -145,3 +170,36 @@ examples:
> > };
> > };
> > };
> > +
> > + - |+
> > + /* Example 5 (SpacemiT distributed IOMMU) */
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > + iommu4: iommu at 1bccd000 {
> > + compatible = "qemu,riscv-iommu", "riscv,iommu";
>
> You cannot use the qemu compatible for your device, you must use a
> specific one for the spacemit k3.
Sure.
>
> Also, why is your version "v1.1"? That should just be "v1", and your
> next version "v2" etc.
I'm still using an old fashioned upstream rule, thanks for the reminder.
>
> pw-bot: changes-requested
OK. Will send a revised patchset later.
Cheers,
Lv
>
> Cheers,
> Conor.
>
> > + reg = <0x1bccd000 0x1000>;
> > + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>, <58 IRQ_TYPE_LEVEL_HIGH>,
> > + <58 IRQ_TYPE_LEVEL_HIGH>, <58 IRQ_TYPE_LEVEL_HIGH>,
> > + <62 IRQ_TYPE_LEVEL_HIGH>, <63 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "civ", "fiv", "ioats-pmiv", "piv",
> > + "ioatc0-pmiv", "ioatc1-pmiv";
> > + interrupt-parent = <&saplic>;
> > + #iommu-cells = <0x01>;
> > + /* SpacemiT T100 features */
> > + global-filter;
> > + vendor-hpm-events = "0x10:pri_page_reqs",
> > + "0x11:ptw_cache_reqs",
> > + "0x12:dtw_cache_reqs",
> > + "0x15:all_trans_reqs",
> > + "0x20:dtw_cache_lkps",
> > + "0x28:s1l0_ptw_cache_lkps",
> > + "0x2A:s1l1_ptw_cache_lkps",
> > + "0x2C:s1l2_ptw_cache_lkps",
> > + "0x2E:s1l3_ptw_cache_lkps",
> > + "0x30:s2l0_ptw_cache_lkps",
> > + "0x32:s2l1_ptw_cache_lkps",
> > + "0x34:s2l2_ptw_cache_lkps",
> > + "0x36:s2l3_ptw_cache_lkps",
> > + "0x38:mtlb_lkps",
> > + "0x3A:utlb_lkps";
> > + };
> > --
> > 2.43.0
> >
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