[GIT PULL] RISC-V updates for v6.19-rc7

[patchwork-bot+linux-riscv at kernel.org]

Hello:

This pull request was applied to riscv/linux.git (fixes)
by Linus Torvalds <torvalds at linux-foundation.org>:

On Sat, 24 Jan 2026 16:21:29 -0700 (MST) you wrote:
> Linus,
> 
> Please pull these RISC-V fixes for v6.19-rc7.
> 
> The notable changes here are the three RISC-V timer compare register
> update sequence patches.  These only apply to RV32 systems and are related
> to the 64-bit timer compare value being split across two separate 32-bit
> registers.  We weren't using the appropriate three-write sequence,
> documented in the RISC-V ISA specifications, to avoid spurious timer
> interrupts during the update sequence; so, these patches now use the
> recommended sequence.  This doesn't affect 64-bit RISC-V systems, since
> the timer compare value fits inside a single register and can be updated
> with a single write.
> 
> [...]

Here is the summary with links:
  - [GIT,PULL] RISC-V updates for v6.19-rc7
    https://git.kernel.org/riscv/c/d91a46d6805a

You are awesome, thank you!
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