[PATCH] riscv: Add macros for software check and hardware error exception codes

[Austin Kim]

The latest RISC-V Privileged specification defines new synchronous
exception codes in the scause register:

   18: Software check
   19: Hardware error

Link: https://docs.riscv.org/reference/isa/priv/supervisor.html
- 12.1.8. Supervisor Cause (scause) Register

Add these macros for future use.

Signed-off-by: Austin Kim <austindh.kim at gmail.com>
---
 arch/riscv/include/asm/csr.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 4a37a9839..5ea875813 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -108,6 +108,8 @@
 #define EXC_INST_PAGE_FAULT	12
 #define EXC_LOAD_PAGE_FAULT	13
 #define EXC_STORE_PAGE_FAULT	15
+#define EXC_SOFTWARE_CHECK	18
+#define EXC_HARDWARE_ERROR      19
 #define EXC_INST_GUEST_PAGE_FAULT	20
 #define EXC_LOAD_GUEST_PAGE_FAULT	21
 #define EXC_VIRTUAL_INST_FAULT		22
-- 
2.34.1