[PATCH v2 0/5] Convert riscv to use the generic iommu page table

Wed Jan 21 17:46:47 PST 2026

Hi Jason,

I tested this patch set on my side with the QEMU-virt machine.
I used the following QEMU command for testing:

  $QEMU/qemu-system-riscv64 \
    -M virt,aia=aplic-imsic,aia-guests=7,iommu-sys=on -m 8G -nographic \
    -bios $OPENSBI_IMAGE \
    -serial mon:stdio -serial null -nographic \
    -device e1000e,netdev=net0 \
    -netdev user,id=net0 \
    -cpu rv64,v=true,vlen=256,ssdbltrp=true,smdbltrp=true \
    -device '{"driver":"virtio-9p-device","fsdev":"share","mount_tag":"host0"}'
\
    -fsdev local,id=share,path=share,security_model=mapped \
    -append 'console=ttyS0 earlycon' \
    -kernel $KERNEL_IMAGE \
    -gdb tcp::6234 \
    -smp 4

The boot log shows that the e1000e is successfully added to IOMMU group 1:

  [    0.752808] pci 0000:00:00.0: Adding to iommu group 0
  [    0.753279] pci 0000:00:01.0: Adding to iommu group 1
  [...]
  [    0.763212] e1000e 0000:00:01.0: enabling device (0000 -> 0002)
  [    0.765241] e1000e 0000:00:01.0: Interrupt Throttling Rate
(ints/sec) set to dynamic conservative mode
  [    0.868120] e1000e 0000:00:01.0 eth0: (PCI Express:2.5GT/s:Width
x1) 52:54:00:12:34:56
  [    0.868740] e1000e 0000:00:01.0 eth0: Intel(R) PRO/1000 Network Connection
  [    0.869087] e1000e 0000:00:01.0 eth0: MAC: 3, PHY: 8, PBA No: 000000-000

In this environment, I used iperf3 to verify that the e1000e functions
correctly. The result shows that the test completed successfully:

  # iperf3 --bind-dev eth0 -c speedtest.uztelecom.uz -t 120 -i 10 -V -Z -p 5203
  iperf 3.20
  Linux buildroot 6.19.0-rc4-00059-g92d6f969eb10 #10 SMP Wed Jan 21
11:06:14 CST 2026 riscv64
  Control connection MSS 1460
  Time: Thu, 22 Jan 2026 01:30:52 GMT
  Connecting to host speedtest.uztelecom.uz, port 5203
  [...]
  [  5] local 10.0.2.15 port 58132 connected to 195.69.189.215 port 5203
  Starting Test: protocol: TCP, 1 streams, 131072 byte blocks,
omitting 0 seconds, 120 second test, tos 0
  [ ID] Interval          Transfer    Bitrate        Retr  Cwnd
  [  5]   0.00-10.01  sec  5.62 MBytes  4.71 Mbits/sec    0    128 KBytes
  [  5]  10.01-20.01  sec  44.0 MBytes  36.9 Mbits/sec    0    128 KBytes
  [...]
  [  5] 110.01-120.05 sec  69.1 MBytes  57.7 Mbits/sec    0    128 KBytes
  - - - - - - - - - - - - - - - - - - - - - - - - -
  Test Complete. Summary Results:
  [ ID] Interval          Transfer    Bitrate        Retr
  [  5]   0.00-120.05 sec   676 MBytes  47.2 Mbits/sec    0             sender
  [  5]   0.00-120.05 sec   675 MBytes  47.2 Mbits/sec                  receiver
  CPU Utilization: local/sender 3.8% (0.0%u/3.8%s), remote/receiver
5.2% (0.7%u/4.6%s)

  iperf Done.

Thank you very much for enabling the generic IOMMU page table mechanism to
support RISC-V IOMMU.

Tested-by: Vincent Chen <vincent.chen at sifive.com>

On Tue, Jan 6, 2026 at 11:07 PM Jason Gunthorpe <jgg at nvidia.com> wrote:
>
> This is a fairly straightforward conversion of the RISC-V iommu driver to
> use the now merged generic iommu page table code.
>
> It brings support for SVNAPOT which is a 64K contiguous page. Otherwise it
> should not change the behavior.
>
> The series disables SADE as the dirty tracking support is not implemented
> in the driver and should be done somewhat differently. The generic code
> gets further along though this does not include the format implementation
> of read and clear dirty.
>
> The format implementation should be able to support the 32 bit option, but
> this does not enable the iommu implementation as there seems to be no user
> today.
>
> It looks like RISCV could support the DYNAMIC_TOP option. It would require
> some additional work on the core side to interact safely with SIGN_EXTEND.
>
> This is on github: https://github.com/jgunthorpe/linux/commits/iommu_pt_riscv
>
> v2:
>  - Rebase to v6.19-rc1
>  - Fix typo in PT_FEAT_RISCV_SVNAPOT_64K
> v1: https://patch.msgid.link/r/0-v1-d3317b0ee398+50-iommu_pt_riscv_jgg@nvidia.com
>
> Jason Gunthorpe (5):
>   iommupt: Add the RISC-V page table format
>   iommu/riscv: Disable SADE
>   iommu/riscv: Use the generic iommu page table
>   iommu/riscv: Enable SVNAPOT support for contiguous ptes
>   iommu/riscv: Allow RISC_VIOMMU to COMPILE_TEST
>
>  drivers/iommu/generic_pt/.kunitconfig        |   1 +
>  drivers/iommu/generic_pt/Kconfig             |   9 +
>  drivers/iommu/generic_pt/fmt/Makefile        |   2 +
>  drivers/iommu/generic_pt/fmt/defs_riscv.h    |  29 ++
>  drivers/iommu/generic_pt/fmt/iommu_riscv64.c |  11 +
>  drivers/iommu/generic_pt/fmt/riscv.h         | 313 +++++++++++++++++++
>  drivers/iommu/riscv/Kconfig                  |   8 +-
>  drivers/iommu/riscv/iommu-bits.h             |   4 +-
>  drivers/iommu/riscv/iommu.c                  | 302 +++---------------
>  include/linux/generic_pt/common.h            |  16 +
>  include/linux/generic_pt/iommu.h             |  11 +
>  11 files changed, 445 insertions(+), 261 deletions(-)
>  create mode 100644 drivers/iommu/generic_pt/fmt/defs_riscv.h
>  create mode 100644 drivers/iommu/generic_pt/fmt/iommu_riscv64.c
>  create mode 100644 drivers/iommu/generic_pt/fmt/riscv.h
>
>
> base-commit: 9ace4753a5202b02191d54e9fdf7f9e3d02b85eb
> --
> 2.43.0
>
>
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