[PATCH] crypto: aegis128: Add RISC-V vector SIMD implementation

kernel test robot lkp at intel.com
Wed Jan 21 09:50:11 PST 2026


Hi Chunyan,

kernel test robot noticed the following build errors:

[auto build test ERROR on herbert-cryptodev-2.6/master]
[also build test ERROR on herbert-crypto-2.6/master linus/master v6.19-rc6 next-20260120]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Chunyan-Zhang/crypto-aegis128-Add-RISC-V-vector-SIMD-implementation/20260121-184354
base:   https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master
patch link:    https://lore.kernel.org/r/20260121101923.64657-1-zhangchunyan%40iscas.ac.cn
patch subject: [PATCH] crypto: aegis128: Add RISC-V vector SIMD implementation
config: riscv-randconfig-001-20260121 (https://download.01.org/0day-ci/archive/20260122/202601220110.ontiS30n-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260122/202601220110.ontiS30n-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601220110.ontiS30n-lkp@intel.com/

All error/warnings (new ones prefixed by >>):

>> crypto/aegis128-rvv.c:21:2: error: call to undeclared function 'kernel_vector_begin'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           kernel_vector_begin();
           ^
>> crypto/aegis128-rvv.c:23:2: error: call to undeclared function 'kernel_vector_end'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           kernel_vector_end();
           ^
   crypto/aegis128-rvv.c:28:2: error: call to undeclared function 'kernel_vector_begin'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           kernel_vector_begin();
           ^
   crypto/aegis128-rvv.c:30:2: error: call to undeclared function 'kernel_vector_end'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           kernel_vector_end();
           ^
   crypto/aegis128-rvv.c:36:2: error: call to undeclared function 'kernel_vector_begin'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           kernel_vector_begin();
           ^
   crypto/aegis128-rvv.c:38:2: error: call to undeclared function 'kernel_vector_end'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           kernel_vector_end();
           ^
   crypto/aegis128-rvv.c:44:2: error: call to undeclared function 'kernel_vector_begin'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           kernel_vector_begin();
           ^
   crypto/aegis128-rvv.c:46:2: error: call to undeclared function 'kernel_vector_end'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           kernel_vector_end();
           ^
   crypto/aegis128-rvv.c:57:2: error: call to undeclared function 'kernel_vector_begin'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           kernel_vector_begin();
           ^
   crypto/aegis128-rvv.c:60:2: error: call to undeclared function 'kernel_vector_end'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           kernel_vector_end();
           ^
   10 errors generated.
--
>> crypto/aegis128-rvv-inner.c:317:10: warning: unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'relax' or 'norelax' [-Winline-asm]
                         ".option  arch,+v\n"
                          ^
   <inline asm>:2:9: note: instantiated into assembly here
   .option arch,+v
           ^
>> crypto/aegis128-rvv-inner.c:318:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vsetivli zero, 0x10, e8, m1, ta, ma\n"
                          ^
   <inline asm>:3:1: note: instantiated into assembly here
   vsetivli        zero, 0x10, e8, m1, ta, ma
   ^
   crypto/aegis128-rvv-inner.c:319:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vle8.v   v0, (%[const0])\n"
                          ^
   <inline asm>:4:1: note: instantiated into assembly here
   vle8.v  v0, (a5)
   ^
   crypto/aegis128-rvv-inner.c:320:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vle8.v   v1, (%[const1])\n"
                          ^
   <inline asm>:5:1: note: instantiated into assembly here
   vle8.v  v1, (s1)
   ^
   crypto/aegis128-rvv-inner.c:321:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vse8.v   v0, (%[block2])\n"
                          ^
   <inline asm>:6:1: note: instantiated into assembly here
   vse8.v  v0, (a1)
   ^
   crypto/aegis128-rvv-inner.c:322:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vse8.v   v1, (%[block1])\n"
                          ^
   <inline asm>:7:1: note: instantiated into assembly here
   vse8.v  v1, (a0)
   ^
   crypto/aegis128-rvv-inner.c:323:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vle8.v   v2, (%[iv])\n"
                          ^
   <inline asm>:8:1: note: instantiated into assembly here
   vle8.v  v2, (a2)
   ^
   crypto/aegis128-rvv-inner.c:324:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vle8.v   v3, (%[key])\n"
                          ^
   <inline asm>:9:1: note: instantiated into assembly here
   vle8.v  v3, (s2)
   ^
   crypto/aegis128-rvv-inner.c:325:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vxor.vv  v0, v0, v3\n"
                          ^
   <inline asm>:10:1: note: instantiated into assembly here
   vxor.vv v0, v0, v3
   ^
   crypto/aegis128-rvv-inner.c:326:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vxor.vv  v1, v1, v3\n"
                          ^
   <inline asm>:11:1: note: instantiated into assembly here
   vxor.vv v1, v1, v3
   ^
   crypto/aegis128-rvv-inner.c:327:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vxor.vv  v2, v2, v3\n"
                          ^
   <inline asm>:12:1: note: instantiated into assembly here
   vxor.vv v2, v2, v3
   ^
   crypto/aegis128-rvv-inner.c:328:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vse8.v   v2, (%[block0])\n"
                          ^
   <inline asm>:13:1: note: instantiated into assembly here
   vse8.v  v2, (s3)
   ^
   crypto/aegis128-rvv-inner.c:329:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vse8.v   v2, (%[kiv])\n"
                          ^
   <inline asm>:14:1: note: instantiated into assembly here
   vse8.v  v2, (s6)
   ^
   crypto/aegis128-rvv-inner.c:330:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vse8.v   v0, (%[block3])\n"
                          ^
   <inline asm>:15:1: note: instantiated into assembly here
   vse8.v  v0, (a3)
   ^
   crypto/aegis128-rvv-inner.c:331:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vse8.v   v1, (%[block4])\n"
                          ^
   <inline asm>:16:1: note: instantiated into assembly here
   vse8.v  v1, (a4)
   ^
   crypto/aegis128-rvv-inner.c:82:10: warning: unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'relax' or 'norelax' [-Winline-asm]
                         ".option  arch,+v\n"
                          ^
   <inline asm>:2:9: note: instantiated into assembly here
   .option arch,+v
           ^
   crypto/aegis128-rvv-inner.c:83:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vsetivli zero, 0x10, e8, m1, ta, ma\n"
                          ^
   <inline asm>:3:1: note: instantiated into assembly here
   vsetivli        zero, 0x10, e8, m1, ta, ma
   ^
   crypto/aegis128-rvv-inner.c:84:10: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
                         "vle8.v   v13, (%[rev32qu16])\n"
                          ^
   <inline asm>:4:1: note: instantiated into assembly here
   vle8.v  v13, (a0)


vim +/kernel_vector_begin +21 crypto/aegis128-rvv.c

    16	
    17	void crypto_aegis128_init_simd(struct aegis_state *state,
    18				       const union aegis_block *key,
    19				       const u8 *iv)
    20	{
  > 21		kernel_vector_begin();
    22		crypto_aegis128_init_rvv(state, key, iv);
  > 23		kernel_vector_end();
    24	}
    25	

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