riscv: hwprobe: add support for RISCV_HWPROBE_KEY_IMA_EXT_1

[Andrew Jones]

On Thu, Nov 27, 2025 at 01:23:35AM -0700, Paul Walmsley wrote:
> We've run out of bits to describe RISC-V ISA extensions in our initial
> hwprobe key, RISCV_HWPROBE_KEY_IMA_EXT_0.  So, let's add
> RISCV_HWPROBE_KEY_IMA_EXT_1, along with the framework to set the
> appropriate hwprobe tuple, and add testing for it.
> 
> Signed-off-by: Paul Walmsley <pjw at kernel.org>
> ---
>  Documentation/arch/riscv/hwprobe.rst          |   4 +
>  arch/riscv/include/asm/hwprobe.h              |   3 +-
>  arch/riscv/include/uapi/asm/hwprobe.h         |   1 +
>  arch/riscv/kernel/sys_hwprobe.c               | 169 +++++++++++-------
>  .../selftests/riscv/hwprobe/which-cpus.c      |  18 +-
>  5 files changed, 120 insertions(+), 75 deletions(-)
> 
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 641ec4abb906..03484a2546da 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -387,3 +387,7 @@ The following keys are defined:
>  
>  * :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which
>    represents the size of the Zicbop block in bytes.
> +
> +* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional
> +  extensions that are compatible with the
> +  :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.

Can we also change the documentation for RISCV_HWPROBE_KEY_IMA_EXT_0
to remove the word 'the' before extensions, i.e. just '...containing
extensions...' rather than '...containing the extensions...'?

Otherwise,

Reviewed-by: Andrew Jones <andrew.jones at oss.qualcomm.com>

Thanks,
drew