[PATCH RFC 01/10] riscv: Standardize extension capitilization

[Andrew Jones]

On Wed, Dec 10, 2025 at 08:13:38AM -0800, Charlie Jenkins wrote:
...
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index 865dae903aa0..b6f5d1a74aec 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -26,14 +26,14 @@
>  /* Mapping between KVM ISA Extension ID & guest ISA extension ID */
>  static const unsigned long kvm_isa_ext_arr[] = {
>  	/* Single letter extensions (alphabetically sorted) */
> -	[KVM_RISCV_ISA_EXT_A] = RISCV_ISA_EXT_a,
> -	[KVM_RISCV_ISA_EXT_C] = RISCV_ISA_EXT_c,
> -	[KVM_RISCV_ISA_EXT_D] = RISCV_ISA_EXT_d,
> -	[KVM_RISCV_ISA_EXT_F] = RISCV_ISA_EXT_f,
> -	[KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h,
> -	[KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i,
> -	[KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m,
> -	[KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v,
> +	[KVM_RISCV_ISA_EXT_A] = RISCV_ISA_EXT_A,
> +	[KVM_RISCV_ISA_EXT_C] = RISCV_ISA_EXT_C,
> +	[KVM_RISCV_ISA_EXT_D] = RISCV_ISA_EXT_D,
> +	[KVM_RISCV_ISA_EXT_F] = RISCV_ISA_EXT_F,
> +	[KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_H,
> +	[KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_I,
> +	[KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_M,
> +	[KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_V,
>  	/* Multi letter extensions (alphabetically sorted) */
>  	KVM_ISA_EXT_ARR(SMNPM),
>  	KVM_ISA_EXT_ARR(SMSTATEEN),
>

Thanks to the case change, we can now also consistently use the
KVM_ISA_EXT_ARR() macro here:

 KVM_ISA_EXT_ARR(A)
 KVM_ISA_EXT_ARR(C)
 KVM_ISA_EXT_ARR(D)
 ...

Thanks,
drew