[PATCH v3 0/3] riscv: fix timer update hazards on RV32

[Naohiko Shimizu]

Thank you very much, Paul.
I really appreciate your quick handling.

Naohiko

On Thu, Jan 15, 2026 at 9:39 AM Paul Walmsley <pjw at kernel.org> wrote:
>
> On Sun, 4 Jan 2026, Naohiko Shimizu wrote:
>
> > This patch series fixes timer register update hazards on RV32 for
> > clocksource, KVM, and suspend/resume paths by adopting the 3-step
> > update sequence recommended by the RISC-V Privileged Specification.
> >
> > Changes in v3:
> > - Dropped redundant subject line from commit descriptions.
> > - Added Fixes tags for all patches.
> > - Moved Signed-off-by tags to the end of commit messages.
> >
> > Changes in v2:
> > - Added detailed architectural background to commit messages.
> > - Added KVM and suspend/resume cases.
> >
> > Naohiko Shimizu (3):
> >   riscv: clocksource: Fix stimecmp update hazard on RV32
> >   riscv: kvm: Fix vstimecmp update hazard on RV32
> >   riscv: suspend: Fix stimecmp update hazard on RV32
> >
> >  arch/riscv/kernel/suspend.c       | 3 ++-
> >  arch/riscv/kvm/vcpu_timer.c       | 6 ++++--
> >  drivers/clocksource/timer-riscv.c | 3 ++-
> >  3 files changed, 8 insertions(+), 4 deletions(-)
>
> Thanks, queued for v6.19-rc.
>
>
> - Paul