[PATCH v3 07/10] riscv: Add RISC-V entries in processor type and ISA strings

[Sunil V L]

Hi Himanshu,

On Fri, Jan 9, 2026 at 2:33 PM Himanshu Chauhan
<himanshu.chauhan at oss.qualcomm.com> wrote:
>
> Add RISCV and RISCV32/64 strings in the in processor type and ISA strings
> respectively. These are defined for cper records.
>
I think it is better to add the reference to the ECR in the commit message.

> Signed-off-by: Himanshu Chauhan <himanshu.chauhan at oss.qualcomm.com>
> ---
>  drivers/firmware/efi/cper.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/firmware/efi/cper.c b/drivers/firmware/efi/cper.c
> index 0232bd040f61..9d591a294327 100644
> --- a/drivers/firmware/efi/cper.c
> +++ b/drivers/firmware/efi/cper.c
> @@ -170,6 +170,7 @@ static const char * const proc_type_strs[] = {
>         "IA32/X64",
>         "IA64",
>         "ARM",
> +       "RISCV",

This should be "RISC-V" as per the ECR.

>  };
>
>  static const char * const proc_isa_strs[] = {
> @@ -178,6 +179,8 @@ static const char * const proc_isa_strs[] = {
>         "X64",
>         "ARM A32/T32",
>         "ARM A64",
> +       "RISCV32",
> +       "RISCV64",

This should be "RV32/RV32E" and "RV64" as per the ECR approved.

Thanks,
Sunil