[PATCH v4 10/11] riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC

[Guodong Xu]

Hi, Yixun and Inochi

On Sat, Jan 10, 2026 at 7:05 PM Yixun Lan <dlan at gentoo.org> wrote:
>
> Hi Guodong,
>
> On 18:00 Sat 10 Jan     , Inochi Amaoto wrote:
> > On Sat, Jan 10, 2026 at 01:18:22PM +0800, Guodong Xu wrote:
> > > SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant.
> > > Add nodes of uarts, timer and interrupt-controllers.
> > >
> > > Signed-off-by: Guodong Xu <guodong at riscstar.com>
> > > ---
> > > v4: Fix missing blank space after commas in compatible string.
> > >     Add m-mode imsic and aplic node.
> > >     Reorder properties in simsic, saplic, mimsic, and maplic nodes
> > >      to match DTS coding style.
> > > v3: Remove "supm" from the riscv,isa-extensions list.
> > > v2: Remove aliases from k3.dtsi, they should be in board DTS.
> > >     Updated riscv,isa-extensions with new extensions from the extensions.yaml.
> > > ---
> > >  arch/riscv/boot/dts/spacemit/k3.dtsi | 590 +++++++++++++++++++++++++++++++++++
> > >  1 file changed, 590 insertions(+)
> > >
> > > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > > new file mode 100644
> > > index 000000000000..a815f85cf5a6
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > > @@ -0,0 +1,590 @@
> ...
> > > +                   d-cache-sets = <256>;
> > > +                   next-level-cache = <&l2_cache0>;
> >
> > > +                   mmu-type = "riscv,sv39";
> >
> > I think this should be riscv,sv48? IIRC K3 supports it.

You are right that the underlying X100 IP core is capable of supporting
both SV39 and SV48. However, not K3.

> >
> I would second the idea here, if the underlying hardware support sv48,
> there is no reason we should limit it in DTS, DT should reflect the actual
> hardware.. if user still prefer to use sv39 for simplicity, a "no4lvl"
> command line argument can be passed.. see
>  arch/riscv/mm/init.c +860 -> set_satp_mode()

I have double-checked with SpacemiT, according to SpacemiT, while the X100
core itself supports both SV39 and SV48, when it was integrated into the K3
SoC, it was specifically configured to support only SV39.

In this case, the K3 SoC's MMU is configured for SV39 only, so mmu-type =
"riscv,sv39" is the correct representation.

Best regards,
Guodong Xu

>
> --
> Yixun Lan (dlan)