[PATCH 2/2] PCI: dwc: Add multi-port controller support

[Niklas Cassel]

On Mon, Jan 05, 2026 at 05:57:55PM +0530, Sumit Kumar wrote:
> The current DesignWare PCIe RC implementation supports only the controller
> (Host Bridge) node for specifying the Root Port properties in an assumption
> that the underlying platform only supports a single root Port per
> controller instance. This limits support for multi-port controllers where
> different ports may have different lane configurations and speed limits.
> 
> Introduce a separate dw_pcie_port structure to enable multi-port support.
> Each Root Port can have independent lane count, speed limit through pcie at N
> child nodes in device tree. Add dw_pcie_parse_root_ports()
> API to parse these child nodes.
> 
> Equalization presets and link width detection currently use common DBI
> space for all the root ports. Per-port DBI space assignment for these
> features will be added in future.
> 
> Signed-off-by: Sumit Kumar <sumit.kumar at oss.qualcomm.com>

Hello Sumit,

Is there a reason why you represent this as a list of ports rather than a
simple array?

The number of ports is known by parsing the device tree, so it should be
static, no?

At least to me, this seem similar to e.g. how a gpio_device has multiple
gpio_descriptors "struct gpio_desc *descs":
https://github.com/torvalds/linux/blob/master/drivers/gpio/gpiolib.h#L68C1-L68C26

A list is usually used for something that is dynamic.
I don't think that the number of ports to a PCIe controller will be dynamic.

I can see that struct qcom_pcie in pcie-qcom.c has struct list_head ports,
but that does not necessarily mean that we need to have a list of ports in
pcie-designware-host.c. (pcie-qcom could also be modified to have an array
of ports if there is a desire for similar design pattern.)


Kind regards,
Niklas