[PATCH 1/3] riscv: clocksource: Fix stimecmp update hazard on RV32

[Naohiko Shimizu]

Hi Anup,

I have just submitted the v2 series with the detailed descriptions as
you suggested.

v2 link: https://lore.kernel.org/lkml/20260103152400.552-1-naohiko.shimizu@gmail.com/T/#u

Regards, Naohiko Shimizu


On Sat, Jan 3, 2026 at 11:46 PM Anup Patel <apatel at ventanamicro.com> wrote:
>
> On Sat, Jan 3, 2026 at 3:16 PM Naohiko Shimizu
> <naohiko.shimizu at gmail.com> wrote:
>
> Please add a detailed commit description about why the
> new way of programming stimecmp is better. Also, explain
> what the current Priv spec says in this context.
>
> >
> > Signed-off-by: Naohiko Shimizu <naohiko.shimizu at gmail.com>
> > ---
> >  drivers/clocksource/timer-riscv.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> > index 4d7cf338824a..cfc4d83c42c0 100644
> > --- a/drivers/clocksource/timer-riscv.c
> > +++ b/drivers/clocksource/timer-riscv.c
> > @@ -50,8 +50,9 @@ static int riscv_clock_next_event(unsigned long delta,
> >
> >         if (static_branch_likely(&riscv_sstc_available)) {
> >  #if defined(CONFIG_32BIT)
> > -               csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
> > +               csr_write(CSR_STIMECMP, ULONG_MAX);
> >                 csr_write(CSR_STIMECMPH, next_tval >> 32);
> > +               csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
> >  #else
> >                 csr_write(CSR_STIMECMP, next_tval);
> >  #endif
> > --
> > 2.39.5
> >
> >
>
> Regards,
> Anup