[PATCH 11/12] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree

[Andrew Lunn]

> +&ethernet {
> +	phy-handle = <&phy0>;
> +	/*
> +	 * YT8531 RGMII timing on this board requires no PHY internal delays.

Please extend this sentence with an explanation why it needs no delay?

There are times this is correct, but it is also mostly wrong. Without
an explanation, i cannot say if this is correct or not.

   Andrew