[PATCH v1 2/2] perf: RISC-V: store available counter mask as bitmap

[Xixin Liu]

Hi Paul,

On Fri, 7 Aug 2026, Paul Walmsley wrote:
> This patch contains several array indexes to element 0 of the cmask
> bitmap, but that element is going to be XLEN bits wide.   Does that
> actually work on RV32 systems?

I built with CONFIG_ARCH_RV32I=y and booted qemu-system-riscv32.
Probe reports 16 firmware and 18 hardware counters.  The available
bitmap is two words: 0xfffffffd then 0x7.  Three bits sit at index 32
and above.

When CFG_MATCH fails on the first word, the same call is retried with
base 32 and the second word.  That is the walk the stop-all path already
used.  Clearing the first word still issues that second call with
base 32.

I also booted qemu-system-riscv64.  Probe reports the same 16 firmware
and 18 hardware counters.  The available bitmap is one word:
0x7fffffffd.  CFG_MATCH and stop-all stay on that word.  Opening a
cycles event from userspace succeeds on both guests.

A legacy-only RV32 kernel sets cycle and instret in the bitmap.  Opening
a cycles event from userspace succeeds there too.

v2 walks every bitmap word for the remaining CFG_MATCH sites, same as
stop-all, with the counter base set to i times BITS_PER_LONG.

Thanks,
Xixin