[PATCH v3 04/16] PCI: dwc: layerscape-ep: Use cached PCIe capability offset

[Frank Li]

On Mon, Jul 20, 2026 at 11:06:07PM +0800, Hans Zhang wrote:
> [You don't often get email from 18255117159 at 163.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> Replace these with dw_pcie_get_pcie_cap(). The hardware is already enabled
> by the driver before ls_pcie_ep_probe() and before the interrupt handler
> runs. dw_pcie_get_pcie_cap() will cache the offset on first call, and
> subsequent calls (including inside dw_pcie_ep_init) will use the cached
> value without re-searching.
>
> Signed-off-by: Hans Zhang <18255117159 at 163.com>
> ---

Reviewed-by: Frank Li <Frank.Li at nxp.com>

> In pci-layerscape-ep, dw_pcie_find_capability() is called in:
>
>   ls_pcie_ep_probe()
>     -> offset = dw_pcie_find_capability()
>     -> pcie->lnkcap = dw_pcie_readl_dbi(offset + PCI_EXP_LNKCAP)
>     -> dw_pcie_ep_init()
>     -> ls_pcie_ep_interrupt_init()
>         -> devm_request_irq(..., ls_pcie_ep_event_handler)
>           -> ls_pcie_ep_event_handler()
>             -> dw_pcie_find_capability()
> ---
>  drivers/pci/controller/dwc/pci-layerscape-ep.c | 9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> index 8936975ff104..b2d0b51df3c5 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -74,7 +74,6 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
>         struct ls_pcie_ep *pcie = dev_id;
>         struct dw_pcie *pci = pcie->pci;
>         u32 val, cfg;
> -       u8 offset;
>
>         val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_DR);
>         ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
> @@ -83,9 +82,6 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
>                 return IRQ_NONE;
>
>         if (val & PEX_PF0_PME_MES_DR_LUD) {
> -
> -               offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> -
>                 /*
>                  * The values of the Maximum Link Width and Supported Link
>                  * Speed from the Link Capabilities Register will be lost
> @@ -93,7 +89,8 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
>                  * that configured by the Reset Configuration Word (RCW).
>                  */
>                 dw_pcie_dbi_ro_wr_en(pci);
> -               dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);
> +               dw_pcie_writel_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP,
> +                                  pcie->lnkcap);
>                 dw_pcie_dbi_ro_wr_dis(pci);
>
>                 cfg = ls_pcie_pf_lut_readl(pcie, PEX_PF0_CONFIG);
> @@ -266,7 +263,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
>
>         platform_set_drvdata(pdev, pcie);
>
> -       offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +       offset = dw_pcie_get_pcie_cap(pci);
>         pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
>
>         ret = dw_pcie_ep_init(&pci->ep);
> --
> 2.34.1
>
>