[PATCH v3 02/16] PCI: dwc: Use cached PCIe capability offset in core

[Manivannan Sadhasivam]

On Mon, Jul 20, 2026 at 11:06:05PM +0800, Hans Zhang wrote:
> Modify the DWC core functions to use the cached pcie_cap offset instead
> of calling dw_pcie_find_capability() each time.
> 
> In the DWC core, dw_pcie_find_capability() is called at several locations:
> - dw_pcie_ep_init_non_sticky_registers()
> - dw_pcie_wait_for_link()
> - dw_pcie_link_set_max_speed()
> - dw_pcie_link_get_max_link_width()
> - dw_pcie_link_set_max_link_width()
> 
> The cached offset is initialized after hardware is ready:
> - In host mode: dw_pcie_host_init() calls pp->ops->host_init() (enables
>   clocks/resets), then dw_pcie_get_pcie_cap() caches the offset.
> - In endpoint mode: the core no longer caches automatically. Instead,
>   drivers must call dw_pcie_get_pcie_cap() after hardware is enabled
>   (e.g., after PERST# deassert).

But you didn't modify all DWC EP drivers to call dw_pcie_get_pcie_cap(). This
can lead to pcie_cap being 0.

> dw_pcie_ep_init_non_sticky_registers()
>   is called after that point, so it can safely use pci->pcie_cap.
> 
> dw_pcie_ep_init_non_sticky_registers() now assumes pci->pcie_cap is
> valid. if not, it prints a warning and skips the operation.

Where is this warning printed?

These are already pointed out by Sashiko. You should go really go through all of
them (not the pre-existing issues) and comment whether the issues are valid or
false positive. For a series touching many controller drivers, this is necessary
to avoid introducing regressions.

I'm not going to merge this series until you fix the real issues Sashiko
reported or mark them as false positive if not valid.

- Mani

-- 
மணிவண்ணன் சதாசிவம்