[PATCH v5 12/17] riscv: dts: spacemit: k1: Add Zic64b ISA extension

[Guodong Xu]

On Wed, 01 Jul 2026 14:00:57 +0000, sashiko-bot at kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Low] Adding a new ISA extension (`zic64b`) to the explicitly deprecated `riscv,isa` devicetree property.
> --
>
> commit a35d1f188ef1737f4ebf996e0483596e27176d0a
> Author: Guodong Xu <docular.xu at gmail.com>
>
> riscv: dts: spacemit: k1: Add Zic64b ISA extension
>
> This commit adds the Zic64b ISA extension to the K1 X60 cores. It updates
> both the riscv,isa-extensions list and the deprecated riscv,isa string
> across all CPU nodes in the device tree.
>
> > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > index 08a0f28d011fe..f179c619f5807 100644
> > --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > @@ -54,12 +54,12 @@ cpu_0: cpu at 0 {
> >  			compatible = "spacemit,x60", "riscv";
> >  			device_type = "cpu";
> >  			reg = <0>;
> > -			riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa = "rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
>
> [Severity: Low]
> This isn't a bug, but the riscv,isa devicetree property is officially
> deprecated in the devicetree bindings. Is it intentional to add the
> new zic64b extension to this legacy string?
>
> The accepted policy generally dictates that new extensions should only be
> added to the riscv,isa-extensions property.

Intentional. k1.dtsi carries both riscv,isa-extensions and the
legacy riscv,isa string in every CPU node, describing the same
hardware. As long as the file keeps both properties, they must list
the same set.

Inconsistency creates confusions to readers.

Guodong