[PATCH] cache: sifive_ccache: Add StarFive JH7110 SoC support

[Dominique Belhachemi]

On Thu, Apr 30, 2026 at 3:14 PM Conor Dooley <conor at kernel.org> wrote:
>
> What's the motivation for enabling the nonstandard cache ops here?
> The driver already binds with the generic sifive compatible on this
> platform, and there's no peripherals currently supported on this
> platform that need non-coherent DMA.

I am using the integrated BXE-4-32 GPU on the JH7110 with Mesa and
Vulkan on a stock Debian system (running headless so far).
To get a simple working setup, I had to patch the powervr driver
module, the device tree (both are easily patchable on the SBC)
and unfortunately, the kernel with the proposed ccache change.

See e.g.
https://github.com/domibel/linux/commit/7240d995571a13d288b5cc52097c4ebb5b339f9b
https://docs.mesa3d.org/drivers/powervr.html

The generic binding alone doesn't help, sifive,ccache0 matches but doesn't pass
QUIRK_NONSTANDARD_CACHE_OPS, so riscv_noncoherent_register_cache_ops()
is never called.

starfive,jh7110-ccache is already documented in
Documentation/devicetree/bindings/cache/sifive,ccache0.yaml .