[PATCH v2] iommu/riscv: Add IOTINVAL after updating DDT/PDT entries

[patchwork-bot+linux-riscv at kernel.org]

Hello:

This patch was applied to riscv/linux.git (fixes)
by Joerg Roedel <joerg.roedel at amd.com>:

On Thu, 22 Jan 2026 22:32:24 +0800 you wrote:
> From: Fangyu Yu <fangyu.yu at linux.alibaba.com>
> 
> Add riscv_iommu_iodir_iotinval() to perform required TLB and context cache
> invalidations after updating DDT or PDT entries, as mandated by the RISC-V
> IOMMU specification (Section 6.3.1 and 6.3.2).
> 
> Fixes: 488ffbf18171 ("iommu/riscv: Paging domain support")
> Signed-off-by: Fangyu Yu <fangyu.yu at linux.alibaba.com>
> Reviewed-by: Andrew Jones <andrew.jones at oss.qualcomm.com>
> 
> [...]

Here is the summary with links:
  - [v2] iommu/riscv: Add IOTINVAL after updating DDT/PDT entries
    https://git.kernel.org/riscv/c/f5c262b54497

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html