[PATCH v7 0/3] riscv: Use GCR.U timer device as clocksource

[Aleksa Paunovic]

On 4/8/26 13:53, Aleksa Paunovic wrote:
> On 3/11/26 14:26, Aleksa Paunovic via B4 Relay wrote:
>> This series adds bindings for the GCR.U timer device and corresponding
>> driver support. Accessing the memory mapped shadow of the mtime register
>> in the GCR.U region should be faster
>> than trapping to M mode each time the timer needs to be read.
>> The timer device does not implement any interrupts, therefore the
>> timer-riscv clockevent implementation should suffice.
>>
>> We tested the patchset both on QEMU and the Boston board with the P8700 bitfile:
>> - Coremark and timer kselftests on QEMU emulating an 8 core CPU
>> - Coremark and timer kselftests on the Boston board with a single core CPU.
> Gentle ping.
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