[PATCH v6 1/4] serial: 8250_dwlib: move DesignWare register definitions to header
Ilpo Järvinen
ilpo.jarvinen at linux.intel.com
Wed Apr 29 03:38:44 PDT 2026
On Wed, 29 Apr 2026, Jia Wang wrote:
> Move the DW_UART_* register offsets and CPR bit/field definitions from
> 8250_dwlib.c into 8250_dwlib.h so they can be shared by 8250_dw and
> 8250_dwlib users.
>
> Add an include guard for 8250_dwlib.h.
>
> Signed-off-by: Jia Wang <wangjia at ultrarisc.com>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com>
> ---
> drivers/tty/serial/8250/8250_dw.c | 11 ------
> drivers/tty/serial/8250/8250_dwlib.c | 49 --------------------------
> drivers/tty/serial/8250/8250_dwlib.h | 67 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 67 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index 94beadb4024d..467755bf0092 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -34,22 +34,11 @@
>
> #include "8250_dwlib.h"
>
> -/* Offsets for the DesignWare specific registers */
> -#define DW_UART_USR 0x1f /* UART Status Register */
> -#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
> -
> #define OCTEON_UART_USR 0x27 /* UART Status Register */
>
> #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
> #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
>
> -/* DesignWare specific register fields */
> -#define DW_UART_IIR_IID GENMASK(3, 0)
> -
> -#define DW_UART_MCR_SIRE BIT(6)
> -
> -#define DW_UART_USR_BUSY BIT(0)
> -
> /* Renesas specific register fields */
> #define RZN1_UART_xDMACR_DMA_EN BIT(0)
> #define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
> diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c
> index b055d89cfb39..8859e66d2d71 100644
> --- a/drivers/tty/serial/8250/8250_dwlib.c
> +++ b/drivers/tty/serial/8250/8250_dwlib.c
> @@ -13,55 +13,6 @@
>
> #include "8250_dwlib.h"
>
> -/* Offsets for the DesignWare specific registers */
> -#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
> -#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */
> -#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */
> -#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
> -#define DW_UART_RAR 0xc4 /* Receive Address Register */
> -#define DW_UART_TAR 0xc8 /* Transmit Address Register */
> -#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */
> -#define DW_UART_CPR 0xf4 /* Component Parameter Register */
> -#define DW_UART_UCV 0xf8 /* UART Component Version */
> -
> -/* Receive / Transmit Address Register bits */
> -#define DW_UART_ADDR_MASK GENMASK(7, 0)
> -
> -/* Line Status Register bits */
> -#define DW_UART_LSR_ADDR_RCVD BIT(8)
> -
> -/* Transceiver Control Register bits */
> -#define DW_UART_TCR_RS485_EN BIT(0)
> -#define DW_UART_TCR_RE_POL BIT(1)
> -#define DW_UART_TCR_DE_POL BIT(2)
> -#define DW_UART_TCR_XFER_MODE GENMASK(4, 3)
> -#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0)
> -#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1)
> -#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2)
> -
> -/* Line Extended Control Register bits */
> -#define DW_UART_LCR_EXT_DLS_E BIT(0)
> -#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1)
> -#define DW_UART_LCR_EXT_SEND_ADDR BIT(2)
> -#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3)
> -
> -/* Component Parameter Register bits */
> -#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0)
> -#define DW_UART_CPR_AFCE_MODE BIT(4)
> -#define DW_UART_CPR_THRE_MODE BIT(5)
> -#define DW_UART_CPR_SIR_MODE BIT(6)
> -#define DW_UART_CPR_SIR_LP_MODE BIT(7)
> -#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8)
> -#define DW_UART_CPR_FIFO_ACCESS BIT(9)
> -#define DW_UART_CPR_FIFO_STAT BIT(10)
> -#define DW_UART_CPR_SHADOW BIT(11)
> -#define DW_UART_CPR_ENCODED_PARMS BIT(12)
> -#define DW_UART_CPR_DMA_EXTRA BIT(13)
> -#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16)
> -
> -/* Helper for FIFO size calculation */
> -#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16)
> -
> /*
> * divisor = div(I) + div(F)
> * "I" means integer, "F" means fractional
> diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
> index 7dd2a8e7b780..2f26f9ecacbe 100644
> --- a/drivers/tty/serial/8250/8250_dwlib.h
> +++ b/drivers/tty/serial/8250/8250_dwlib.h
> @@ -1,11 +1,76 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /* Synopsys DesignWare 8250 library header file. */
>
> +#ifndef _SERIAL_8250_DWLIB_H_
> +#define _SERIAL_8250_DWLIB_H_
> +
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> #include <linux/io.h>
> #include <linux/types.h>
>
> #include "8250.h"
>
> +/* Offsets for the DesignWare specific registers */
> +#define DW_UART_USR 0x1f /* UART Status Register */
> +#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
> +#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
> +#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */
> +#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */
> +#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
> +#define DW_UART_RAR 0xc4 /* Receive Address Register */
> +#define DW_UART_TAR 0xc8 /* Transmit Address Register */
> +#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */
> +#define DW_UART_CPR 0xf4 /* Component Parameter Register */
> +#define DW_UART_UCV 0xf8 /* UART Component Version */
> +
> +/* Interrupt ID Register bits */
> +#define DW_UART_IIR_IID GENMASK(3, 0)
> +
> +/* Modem Control Register bits */
> +#define DW_UART_MCR_SIRE BIT(6)
> +
> +/* Line Status Register bits */
> +#define DW_UART_LSR_ADDR_RCVD BIT(8)
> +
> +/* UART Status Register bits */
> +#define DW_UART_USR_BUSY BIT(0)
> +
> +/* Transceiver Control Register bits */
> +#define DW_UART_TCR_RS485_EN BIT(0)
> +#define DW_UART_TCR_RE_POL BIT(1)
> +#define DW_UART_TCR_DE_POL BIT(2)
> +#define DW_UART_TCR_XFER_MODE GENMASK(4, 3)
> +#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0)
> +#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1)
> +#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2)
> +
> +/* Receive / Transmit Address Register bits */
> +#define DW_UART_ADDR_MASK GENMASK(7, 0)
> +
> +/* Line Extended Control Register bits */
> +#define DW_UART_LCR_EXT_DLS_E BIT(0)
> +#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1)
> +#define DW_UART_LCR_EXT_SEND_ADDR BIT(2)
> +#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3)
> +
> +/* Component Parameter Register bits */
> +#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0)
> +#define DW_UART_CPR_AFCE_MODE BIT(4)
> +#define DW_UART_CPR_THRE_MODE BIT(5)
> +#define DW_UART_CPR_SIR_MODE BIT(6)
> +#define DW_UART_CPR_SIR_LP_MODE BIT(7)
> +#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8)
> +#define DW_UART_CPR_FIFO_ACCESS BIT(9)
> +#define DW_UART_CPR_FIFO_STAT BIT(10)
> +#define DW_UART_CPR_SHADOW BIT(11)
> +#define DW_UART_CPR_ENCODED_PARMS BIT(12)
> +#define DW_UART_CPR_DMA_EXTRA BIT(13)
> +#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16)
> +
> +/* Helper for FIFO size calculation */
> +#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16)
> +
> struct dw8250_port_data {
> /* Port properties */
> int line;
> @@ -38,3 +103,5 @@ static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
> else
> writel(reg, p->membase + offset);
> }
> +
> +#endif /* _SERIAL_8250_DWLIB_H_ */
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen at linux.intel.com>
--
i.
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