[PATCH v4 2/4] serial: 8250_dw: build Renesas RZN1 CPR value from DW_UART_CPR_* definitions

[Jia Wang]

On 2026-04-24 18:16 +0300, Andy Shevchenko wrote:
> On Fri, Apr 24, 2026 at 05:09:46PM +0300, Ilpo Järvinen wrote:
> > On Fri, 24 Apr 2026, Andy Shevchenko wrote:
> > > On Fri, Apr 24, 2026 at 02:38:56PM +0300, Ilpo Järvinen wrote:
> > > > On Fri, 24 Apr 2026, Jia Wang wrote:
> 
> ...
> 
> > > > Hmm, maybe there should also be macro also for this one which takes the 
> > > > fifosize as input and converts it to CPR field vlaue (effectively, the 
> > > > macro is an inverse of DW_UART_CPR_FIFO_SIZE()). It would be more readable 
> > > > than the literal.
> > > 
> > > But this can be done separately, right?
> > 
> > It's logically part of the cpr_value literal to defines conversion (of 
> > course one could introduce it in own patch without users but I don't see 
> > much benefit from that).
> 
> No objections.
> 
> > > > Also include BUILD_BUG_ON(!IS_ALIGNED(fifosize, 16) + bounds checks) 
> > > > inside that macro to catch invalid fifo sizes (+ don't forget the 
> > > > necessary headers for those two new things).
> > > 
> > > Hmm... Some devices may have FIFO = 8 or 4 bytes (Intel Quark IIRC has less
> > > than 16 and it's DW IP).
> > 
> > Perhaps but according the DW databook I've at hand, there are no values in 
> > FIFO_MODE field for such FIFO sizes. So what would CPR contain in those
> > cases for FIFO_MODE field?
> 
> On real HW it returns 0s for all registers above 0x07 (multiplied by 4 as
> a stride). But I also checked the values of xmit_fifo_size and it shows 16.
> What 8 is it is the DMA max_burst. Hence the proposed assertion should work.
> 

Thanks for the discussion and clarification. I'll add the macro
DW_UART_CPR_FIFO_MODE_FROM_SIZE() in 8250_dwlib.h (in patch 2) with the
suggested build‑time checks (using BUILD_BUG_ON_ZERO for bounds validation),
 and update patch 4 to use it.

> -- 
> With Best Regards,
> Andy Shevchenko
> 
> 
> 

Best Regards,
Jia Wang