[PATCH v5 4/5] riscv64: dts: sophgo: add SG2000 dtsi

[Gui-Dong Han]

On Fri, Apr 3, 2026 at 7:16 PM Joshua Milas <josh.milas at gmail.com> wrote:
>
> Adds sg2000.dtsi on the RISCV side.
>
> Signed-off-by: Joshua Milas <josh.milas at gmail.com>

Tested-by: Gui-Dong Han <hanguidong02 at gmail.com>
Reviewed-by: Gui-Dong Han <hanguidong02 at gmail.com>

> ---
>  arch/riscv/boot/dts/sophgo/sg2000.dtsi | 53 ++++++++++++++++++++++++++
>  1 file changed, 53 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2000.dtsi
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2000.dtsi b/arch/riscv/boot/dts/sophgo/sg2000.dtsi
> new file mode 100644
> index 0000000000000..412adacc00576
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2000.dtsi
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/pinctrl/pinctrl-sg2000.h>
> +#include "cv180x-cpus.dtsi"
> +#include "cv180x.dtsi"
> +#include "cv181x.dtsi"
> +
> +/ {
> +       compatible = "sophgo,sg2000";
> +
> +       memory at 80000000 {
> +               device_type = "memory";
> +               reg = <0x80000000 0x10000000>;
> +       };
> +
> +       soc {
> +               interrupt-parent = <&plic>;
> +               dma-noncoherent;
> +
> +               pinctrl: pinctrl at 3001000 {
> +                       compatible = "sophgo,sg2000-pinctrl";
> +                       reg = <0x03001000 0x1000>,
> +                             <0x05027000 0x1000>;
> +                       reg-names = "sys", "rtc";
> +               };
> +
> +               clk: clock-controller at 3002000 {
> +                       compatible = "sophgo,sg2000-clk";
> +                       reg = <0x03002000 0x1000>;
> +                       clocks = <&osc>;
> +                       #clock-cells = <1>;
> +               };
> +
> +               plic: interrupt-controller at 70000000 {
> +                       compatible = "sophgo,sg2000-plic", "thead,c900-plic";
> +                       reg = <0x70000000 0x4000000>;
> +                       interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> +                       interrupt-controller;
> +                       #address-cells = <0>;
> +                       #interrupt-cells = <2>;
> +                       riscv,ndev = <101>;
> +               };
> +
> +               clint: timer at 74000000 {
> +                       compatible = "sophgo,sg2000-clint", "thead,c900-clint";
> +                       reg = <0x74000000 0x10000>;
> +                       interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> +               };
> +       };
> +};
> --
> 2.53.0
>